HSSTP Description

The High Speed Serial Trace Port [HSSTP] specification uses the connector defined in the HSSTP specification, the Aurora protocol developed by Xilinx and the electrical interface defined by XAUI. Refer to the main HSSTP page covering the standard.

Four dual-row connector sizes are allowed; 22-pins, 34-pins, 46-pins and 70-pins. The HST-34 connector [covered here], provides six differential transmit pairs, a Vsense line, five JTAG pins, six Vendor I/O pins, a Reset line and an optional differential clock line.
Ground pins are also supplied per differential pair, which are longer and mate first.
The Vendor I/O pins are SoC specific and are not defined in the HSSTP specification.
The pinout variations are provided below, shown by number of pins.

HSSTP Pinouts

Simplex HST-S34
17 x 2
Pin NumSignal name Signal namePin Num
LatchGND GNDLatch
1TX0+ VIO (Vsense)2
3TX0- TCK4
7TX1+ TDI8
9TX1- TDO10
13TX2+ Vendor I/O 014
15TX2- Vendor I/O 116
17GND Vendor I/O 218
19TX3+ Vendor I/O 320
21TX3- Reset22
25TX4+ CLK+26
27TX4- CLK-28
31TX5+ Vendor I/O 432
33TX5- Vendor I/O 534
LatchGND GNDLatch

HSSTP Connector Pinout Variants

As shown more lanes are added as the connector size increases.
Larger connectors add more Transmit or Receive pairs.
This connector adds 2 additional TX pairs & 2 Vendor I/O lines.

Simplex 11 x 2 HSSTP, 4 differential TX lines.
Simplex 17 x 2 HSSTP, 6 differential TX lines.
Simplex 23 x 2 HSSTP, 8 differential TX lines.
Duplex 11 x 2 HSSTP, 2 differential TX lines, 2 differential RX lines.
Duplex 17 x 2 HSSTP, 4 differential TX lines, 2 differential RX lines.
Duplex 23 x 2 HSSTP, 4 differential TX lines, 4 differential RX lines.
Duplex 35 x 2 HSSTP, 8 differential TX lines, 4 differential RX lines.

The latches are used to secure the connector and are not pins.

Simplex Operation
HST-S34 Size
Transmit Only

PC motherboard

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Modified 1/15/12
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