HSSTP Description

The High Speed Serial Trace Port [HSSTP] specification uses the connector defined in the HSSTP specification, the Aurora protocol developed by Xilinx and the electrical interface defined by XAUI. Refer to the main HSSTP page covering the standard.

Four dual-row connector sizes are allowed; 22-pins, 34-pins, 46-pins and 70-pins. The HST-D22 connector, provides four differential pairs [2 transmit and 2 receive pairs], a Vsense line, five JTAG pins, four Vendor I/O pins [optional] and a Reset line.
Ground pins are also supplied per differential pair, which are longer and mate first.
The Vendor I/O pins are SoC specific and are not defined with the HSSTP specification.
There is no requirement to use the four vendor pins.
The JTAG TRST pin and Rest pin is also optional.
The pinout variations are provided below, shown by connector size & function.

HSSTP Pinouts

Duplex HST-D22
11 x 2
Pin NumSignal name Signal namePin Num
LatchGND GNDLatch
1TX0+ VIO (Vsense)2
3TX0- TCK4
7TX1+ TDI8
9TX1- TDO10
13RX0+ Vendor I/O 014
15RX0- Vendor I/O 116
17GND Vendor I/O 218
19RX1+ Vendor I/O 320
21RX1- Reset22
LatchGND GNDLatch

HSSTP Connector Pinout Variants

Simplex 11 x 2 HSSTP, 4 differential TX lines.
Simplex 17 x 2 HSSTP, 6 differential TX lines.
Simplex 23 x 2 HSSTP, 8 differential TX lines.
Duplex 11 x 2 HSSTP, 2 differential TX lines, 2 differential RX lines.
Duplex 17 x 2 HSSTP, 4 differential TX lines, 2 differential RX lines.
Duplex 23 x 2 HSSTP, 4 differential TX lines, 4 differential RX lines.
Duplex 35 x 2 HSSTP, 8 differential TX lines, 4 differential RX lines.

The latches are used to secure the connector and are not pins.

Duplex refers to having both transmit and receive pairs per lane.
The interface is able to transmit and receive simultaneously.

Duplex Operation
HST-D22 Size
2 Differential Transmit lanes
2 Differential Receive Lanes

PC motherboard

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Modified 1/16/12
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