This is a subdivision of the main alphabetic bus listing. Buses designed to operate between Integrated Circuits [ICs] are listed below. I do not list micro-processor [uP] buses, uP buses may only be used with a particular processor chip. However, many of the buses listed do interface to microcontrollers and microprocessor peripheral chips. The IC buses listed are generic and may be used with any IC or component. IC buses are also called Chip-to-Chip buses, or Interchip Communications. IC buses normally can't drive cable or backplane buses, the load capacitance is to high and bus length is to long. In some cases the application for the bus is also provided with the description.
1-Wire {Originally developed as a processor to memory chip-to-chip interconnect found on Maxim ICs, and now allowed to operate over cable interfaces}
AGP Bus {Accelerated Graphics Port, Computer Video bus. AGP 8x uses a 533MHz clock with 32 bytes/clock, and has a Bandwidth of 2.1GB/s [0.8V signal swing]. The AGP bus is used mainly between the microprocessor and the video peripheral chips. The AGP bus is in the process of being replaced bu the Serial PCI bus.}
BIF Bus {Multiplexed Bus Interface provides a byte-wide interface to the CSI bus which allows devices using a CSI bus to support legacy devices. The BIF bus multiplexes an 8-bit data bus and 8-bit address bus (lower byte). The upper byte address bus is always passed. The bus also has an OE line, an ALE line (Address or Data is valid), a RD (enable), and WR (enable) line. The BIF bus was developed by Triscend}
C-Bus {and C-Bus II was developed by Corollary Inc. as a multiprocessing chip set architecture used with motherboards with more then one linked processor [4-way and 8-way systems]. Corollary Inc. was purchased by Intel in 1997.}
CFI {Common Flash Interface [CFI]is a published, standardized data structure that may be read from a flash memory device. Looks like it was introduced in the late 90's. The CFI bus provides information about the device, type, manufacturer. The physical interface is the same as the IC uses for all other I/O}
CSA Bus [Communication Streaming Architecture] (Intel Corp. uses the [proprietary] CSA Architecture which is based on the HubLink Architecture. CSA provides a bi-directional bandwidth throughput of 266 MB per second (2 Gbps). CSA is a dedicated bus that connects to the Memory Controller Hub (MCH) on the Chipsets.)
CSI Bus {Configurable System Interconnect bus; The CSI bus consists of a 32-bit address bus and a 32-bit data bus running at transfer rates of 265MB/s. The data rate is 40MBps with an 8 bit wide data bus, but expendable to 32 bits (may also be 128 bits). The CSI bus supports a 32 bit address bus, an 8-bit data read bus, an 8-bit data write bus, clock line, control signals, and address section lines. The CSI bus was developed by Triscend, as a proprietary, scalable, processor-independent interface for its Embedded SOC 8032/8051 processors.}
CSI Bus {Common System Interface; A point-to-point processor interconnect being developed by Intel to replace their processor front side bus interface. May also be called the QuickPath Interconnect}
EIB {Element Interconnect Bus. The EIB is a communication bus internal to a Cell processor which connects the various on-chip system elements.}
EMIF; (External Memory Interface) A 16-bit IC bus used on DSP's from TI for asynchronous data transfers to memory or other devices.
EV6 {The Alpha EV6 bus operates at speeds of 40MHz to 400MHz. The EV6 interface was developed for EV6 alpha processors and for a time was also used with AMD processors, but was drop in 2001.}
FC Bus {Fibre Channel [FC] Bus description. A bi-directional interface operating up to 1.0625Gbps running over fiber or copper.}
Flexbus {was developed to connect SONET/SDH physical layer (PHY) framer and mapper ICs to link layer devices such as SARs and network processors; for asynchronous transfer mode (ATM), packet over SONET (POS), and Ethernet. Flexbus 3 operates at 2.5Gbps (OC-48); Flexbus 4; SPI-4 operates at 10Gbps (OC-192).}
FSB (Front Side Bus] Bus provides an interface between the processor and Northbridge chipset in personal computers. The Intel Pentium class of processors use a FSB and Northbridge chipset combination while AMD processors have an integrated on-board Northbridge like interface. The AMD processor use the HyperTransport interface instead of a FSB interface. Processors communicate over the FSB to the Northbridge chipset, the Northbridge then communicates with the memory ICs and other PC buses [PCI, AGP].)
GE Bus {Gigabit Ethernet [GE] Bus description. Ethernet running over fiber or twisted wire operating at 1000Mbps.}
GMII Bus (Gigabit Media Independent Interface] Bus is an 8-wire chip-to-chip bus. RGMII Bus, for Reduced Gigabit Media Independent Interface uses only 4-wires. XGMII Bus uses SSTL_2 interface levels. provides an optional interconnection between the Media Access Control (MAC) sublayer and the Physical layer (PHY) of 10 Gigabit Ethernet. The interface provides two separate 32-bit data paths (TXD 31:0, RXD31:0) each with 4-bit data delimiters (TXC 3:0 , RXC 3:0) which are synchronous to their respective clock (TX_CLK, RX_CLK) and operate at 156.25 MHz ± 0.01%. GMII may be defined in the 802.3 standard, but I have not verified that.)
GPI Bus {Generic Packet Interfaces [GPI] Bus. GPI-8/16/32}
GPI/O {General Purpose input/Output is not a bus but a group I/O extending out of a uP or Controller chip. GPI/O is not the same as the GPI bus.}
HIC Bus (Heterogeneous Interconnect, builds a scalable parallel system using a pair(s) of unidirectional lines between Chip-to-Chip ICs. HIC is also a board or Chassis bus. The HIC bus is defined by the IEEE-1355 specification.)
HSIC Bus (An LVCMOS implementation of USB for Chip-to-Chip interfaces. One bus speed of 480Mbps, over a 10cm trace.)
HMVIP Bus {High-Speed Multi Vendor Interface Protocol [HMVIP] Bus. May also be H-MVIP}
HubLink Bus (Intel Corp. uses the [proprietary] HubLink [HL] architecture in its Intel 8xx chipsets, as a chip-to-chip interface. I believe HubLink 1.0 was an 8 bit wide bus running at 66MHz. HL 1.5 is 8-bits wide and quad pumped at 133 MHz with a bandwidth of 532 Mbps, and is used to connect the MCH to the ICH. HL 2.0 is 16-bits wide and quad pumped at 133 MHz for a theoretical bandwidth of 1.064 Gbps. The faster HL 2.0 interface connects the MCH [Memory Controller Hub] to the PCI-X and IBA bridges. HubLink is now known as the Hub Interface. The latest Hublink interface runs with a maximum throughput of 266 MB per second, roughly 2.2 Gbps.)
HyperTransport Bus (Uses 2, 4, 8, 16 or 32 bits [in each direction]. Data rate is 800MBs/per 8 bit pair(s) with a 400MHz clock. The HyperTransport Bus uses LVDS interface as it's electrical interface)
I2C Bus {The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Three speed modes are specified: Standard; 100kbps [Bits per Second], Fast mode; 400kbps, High speed mode 3.4Mbps all with a maximum bus capacitance of 400pF. I2C, due to its two-wire nature (one clock, one data) can only communicate half-duplex. A new Fast Mode Plus speed is also defined}
I2O Bus (Intelligent Input/Output [or Intelligent I/O] Bus was designed to eliminate I/O bottlenecks by utilizing special I/O processors [IOPs] to off-load work. It was more a Software driver architecture spec then hardware bus. The specification was released in 1997, looks like work on the spec stopped in 2000.)
I2S Bus (Inter-IC Sound [I2S] is a serial bus designed for digital audio devices. The I2S design handles audio data separately from clock signals. An I2S bus design consists of three serial bus lines.
IC_USB (The printed wiring board implementation of USB, over a 10cm trace.)
IP Core Buses {Intellectual Property [IP] Bus or System-On-Chip [SoC] Buses are used to connect pre-designed modules [IP's] used in FPGAs, PLDs, or ASICs}
JTAG Bus {Serial four wire test bus used to 'Boundary-Scan' IC's; at the chip level [JTAG: Joint Test Action Group]}
LPC Bus {Low Pin Count Bus. The LPC Interface allows the legacy I/O motherboard components, typically integrated in a Super I/O chip, to migrate from the ISA/X-bus to the LPC Interface. The LPC Interface Specification describes memory, I/O and DMA transactions, and uses the PCI 33MHz clock. LPC was developed by Intel.}
Memory Interface Buses (A few different interface
standards are used for memory buses, these include: High Speed
Transceiver Logic [HSTL], HSTL-18, and HSTL-15, SSTL, LVCMOS and others.
PC memory buses operate between the North bridge and memory module
expansion sockets. LVCMOS logic was used for interfaces running at or
under 100MHz, higher speed buses require other logic standards:
HSTL [High-Speed Transceiver Logic] is based on EIA-JESD8-6. HSTL
may be single ended or differential ended, using 1.5v supplies. HSTL is
used with DDR-SSRAM and QDR-SRAM modules. There are four classes of HSTL
I/II/III/ and IV. HSTL 1.5v: Vcc=1.5v, VIH=0.85, Vref=0.75v,
Vil=0.65v
SSTL
Stub-Series-terminated logic [SSTL-2 operates at 2.5v, SSTL-18 operates
at 1.8v, SSTL3 operates at 3.3v]. SSTL [JESD8-9] is optimized for the
PC's main memory banks, which have long stubs off the motherboard bus due
to the DIMM routing traces. Class I offers Lower power dissipation, Lower
Drive, Max current 7.6mA . Class II provides higher power dissipation,
Higher drive and max current of 15.2mA
Rambus Signaling Levels: Single-ended open drain, 800MHz switching
speed, 900mV swing.
DRSL [Differential Rambus Signaling Levels]: Differential, 3.2GHz
(per pair), 200mV swing. Eight data words are sent per system clock
(400MHz). The system clock is up-converted to 1.6GHz on chip. Memory
sticks are called XDR, or XDIMM. XDR is 16 bits wide at a 3.2GHz
signalling rate, so you have an aggregate bandwidth of 6.4GBps. A module
can have eight chips, or nine with ECC. 8 * 6.4 = 51.2.
CCT [Center Tap Terminated] Differential bus using 3.3 volt logic
levels, and a 1.5 volt termination level. Memory buses defined here are
electrical only, no protocol is defined.)
MBus (MBus is a circuit-switched, cache-coherent shared-memory interface used with SPARC-architecture CPUs, Sun Microsystems. MBus ran at 50MHz and is OBSOLETE.)
MCBSP {TI DSP serial Bus; Multichannel Buffered Serial Port}
MI Bus (MI Bus [Motorola Interconnect] is a serial [Single wire] communications protocol with one Master and many Slaves. The Master sends address and data [the Push Field] to all slaves on the bus. The slave with the same address responds with the information requested [the Pull Field]. The Push field contains a Start bit [low for 3 bit times], a synchronization bit [bi-phase encoded 0], a data field [5 bits bi-phase encoded], and an address field [3 bits bi-phase encoded]. The Pull field contains a synchronization bit [bi-phase encoded 1], the data field [3 bits encoded NRZ], and a End of frame field [~ 3 cycles of a 20KHz square wave]. The single wire line operates between Logic 0 [0.3v maximum], and Logic 1 [+5 volts].)
MI interface (Serial interface, part of an IEEE802.3 interface)
MICROWIRE Bus {MICROWIRE is a 3Mbps [full-duplex] serial 3-wire interface standard defined by National Semiconductor. The MICROWIRE protocol is essentially a subset of the SPI[tm] interface, CPOL = 0 and CPHA = 0. Microwire is a serial I/O port on microcontrollers, so the Microwire bus will also be found on EEPROMs and other Peripheral chips.}
MPI Bus {The serial MicroProcessor Interface [MPI] bus consists of a bidirectional [three-state] data line [DIO], and a Clock line [DCLK]. The clock frequency is 4.096MHz. The MPI bus is a synchronous Master/Slave serial bus. Using 8 bit words, MSB is transmitted first}
MTM Bus {Serial five wire Test and Maintenance Bus used to 'Boundary-Scan' cards; at the board level. The MTM bus tests at the board level, while JTAG [listed above] tests at the chip or IC level.}
MuTIOL (Silicon Integrated Systems Corp. [SIS] uses MuTIOL as a Proprietary Interconnect between it's North and South bridge chips. MuTIOL [Multi-threaded I/O Link] is a 16-bit 266MHz [533MB/s Bandwidth] bi-directional data bus.)
ONFI { Open NAND Flash Interface. An IC bus for NAND Flash chips}
PCI Bus {The Peripheral Component Interface 'PCI' [Parallel] Bus was originally developed as a local bus expansion for the PC. The first version of the PCI bus ran at 33MHz with a 32 bit bus (133MBps), the current version runs at 66MHz with a 64 bit bus. The PCI bus operates either synchronously or asynchronously with the "mother Board bus rate: The page contains the PCI connector Pin-Outs. The PCI bus uses normal CMOS logic voltage levels.}
PC/104 Bus {The PC/104-Plus Bus, and the PCI/104 buses also use the PCI bus in an embedded PC bus format. The boards stack on top of each other. The PCI/104-Plus and PCI/104 standard only relates to the 33MHz PCI bus. The standard does not support 66MHz PCI. The PC/104 bus is really a Board-to-Board standard}
PCI-X Bus {The Peripheral Component Interface [PCI-X] addendum is an enhancement to the current 64 bit 66MHz PCI bus specification. The minimum clock speed for PCI-X is 66MHz [PCI-X 66]. Additional bus speeds include: PCI-X 133, PCI-X 266 and PCI-X 533 providing up to 4.3GBps [PCI-X 1066 in the works]. PCI-X is backwards compatible with PCI}
PCI Express Bus {Serial PCI Bus uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [Rx / Tx]. Using 8B/10B encoding, and Supporting 1x, 2x, 4x, 8x, 12x, 16x, 32x bus widths. PCIe is set to replace the Parallel PCI bus; PCI, and PCI-X}
PMBus {Power management Bus uses the same physical layer as the SMBus}
POS-PHY Level 3 Bus (Interface defines operations between Physical Layer Devices (ATM, POS and GigE framers) and Link Layer devices (ATM, IP and GigE forwarding devices) at the OC-48 (2.488 Gbps) aggregate line rate. The POS-PHY Level 3 [PL3] interface has since been standardized at the ATM Forum (AF-PHY-0143.000) and at the Optical Internetworking Forum (OIF2000.008.3)}
QuickPath Bus {Intel uP interface, known internally as the Common System Interface (CSI), is explicitly designed to accommodate integrated memory controllers and distributed shared memory. QuickPath is a point-to-point processor interconnect being developed by Intel for their new generation processors.}
RapidIO {An LVDS bus as the electrical interface. RapidIO is suitable for chip-to-chip and board-to-board communications, using a full duplex interface with either an 8-bit or 16-bit [unidirectional] Input and Output @ 10Gbps}
SBI Bus {Scalable Bandwidth Interconnect [SBI] Bus. The SBI term is also used to indicate the "SBus interface"}
SCI Bus {Serial Communications Interface 'SCI' is an asynchronous serial communications bus used between uP [CPUs] and peripheral devices [EPROMs for example]. Two signal lines are used with SCI: TXD [Transmit], RXD [Receive]. The two wire bus operates in full Full-duplex [transmitting and receiving at the same time]. SCI uses either an 8 or 9 bit data format, with data being sent NRZ [non-return-to-zero] encoding. }
SDRAM Bus {SDRAM, DDR, RDRAM and other memory ICs use one of the logic interfaces listed above under Memory Interface Buses}
SensorPath {Power management Bus for Motherboards using just one wire, developed by National Semiconductor}
SFI-4 Bus {Developed by the Optical Internetworking Forum [OIF] uses a 16 bit LVDS interface in OC-192 SONET}
SMbus {System Management Bus is a two wire interface which is based on the I2C bus. The 2 lines are called SMBCLK, and SMBDAT and operate at a frequency of 100KHz. SMbus is used to communicate between ICs, Temperature Sensors, Smart Battery Charges, and 'Smart' batteries. SMLink is an optional SMBus link for external system management ASIC or LAN controllers. Typically, SMBus is powered by the 3.3V power plane, while SMLink is powered by the 3.3V Standby power plane. Systems that implement standby voltages use the isolation to separate devices that can wake up a sleeping system from those that cannot.}
SMIC {Server Management Interface Chip}
SoC / IP Core Buses {System-On-Chip [SoC] or Intellectual Property [IP] Buses connect pre-designed modules [IP's] used in FPGAs, PLDs, or ASICs. With a buffer, these buses may show up outside an FPGA, making it an IC-to-IC bus.}
SPI Bus {Serial Peripheral Interface [SPI-bus] is a 4-wire [full-duplex] serial communications interface used by many microprocessor peripheral chips. The Serial Peripheral Interface [SPI] circuit is a synchronous serial data link operating a 1 megabaud]}
SPI-3 Bus {SPI-4 is a standard interface for 10Gbps point-to-point connections between two chips, OC-48 rates}
SPI-4 Bus {SPI-4 is a standard interface for 10Gbps point-to-point connections between two chips, OC-192 rates}
SSI Bus {The Synchronous Serial Interface [SSI] bus consists of four signals; SCLK, SDATA, SDEN0, and SDEN1. SDATA is a bidirectional [three-state] data line which requires a pull-up or pull-down resistor. Data is sent in 8 bit bytes, LSB first. The SCLK signal is only active during transfers. Data is clocked out on the falling edge and clock in on the rising edge [of the Master]. The other two pins SDEN0 and SDEN1 are enable pins, active high.}
SSTL {Stub-Series-terminated logic [SSTL-2 operates at 2.5v, SSTL-18 operates at 1.8v, SSTL3 operates at 3.3v}
SysAD Bus{The System Address Data [SysAD] bus is a bi-directional multiplexed address and data bus running at 133MHz for processor-to-peripheral communications. The SysAD bus may found next to the SysCmd bus. The SysAD bus uses either 32/64 bits for address and data, 8 bits for the check bus [SysADC]. The SysAD bus is used on the MIPS class of processors.}
SysADC Bus{The System Address Data Check [SysADC] bus is an 8 bit interface used with the SysAD bus. The SysADC bus is used on the MIPS class of processors.}
SysCmd Bus{The System Command [SysCmd] bi-directional bus transmits information about the data on the SysAD bus for processor-to-peripheral communications. The 9-bit SysCmd bus may found next to the SysAD bus on the MIPS class of processors and indicates if address or data resides on the SysAD bus.}
TBI Bus{Telecom Bus Interface [TBI]. TBI is a parallel interface used for chip-to-chip communication on SONETSDH line cards}
TBI Bus {Ten Bit Interface [TBI] Bus. A bus consisting of 10 receive bits, 10 transmit bit, and control lines. The Ten Bit Interface is used in combination with 1000Base-X interfaces.}
UMI {Unified Media Interface, a term used by AMD for a four-lane PCIe connection between a chip-set and processor.}
V-Link (VIA Technologies, Inc. uses V-Link as a narrow high-speed local interface between its north and south bridge chips that can sustain at least 266MB/s peak burst bandwidth. 8X V-Link provides a dedicated 133MHz quad-pumped bus between the North and South Bridge, freeing up the PCI bus to deal strictly with peripheral devices and providing aggregate transfer of 533MB/s. Ultra V-Link Bus supports data throughput speeds up to 1066 MB/s; 16-bit at 66MHz. V-Link is part of V-MAP [Modular Architecture Platform])
VLYNQ (Texas Instruments uses the proprietary VLYNQ bus in it's broadband products, such as modems and wireless local area networks (WLANs); voice broadband processors, digital media processors, and OMAP media processor chips. Licensing agreements for VLYNQ may be obtained from TI.)
XAUI Bus {Ten Attachment Unit Interface [XAUI] Interface. 10 Gigabit Ethernet. Supports 10 Gbps using four transmit and four receive lanes; each lane encoding data with an 8B/10B code for differential serial transmission and operating at 3.125 GigaBaud. XAUI reduces 10 Gigabit Ethernet's 72 pin XGMII to 16 pins, enabling higher density and lower cost switch chips and optical transceiver devices. XAUI is also used with 10GFC}
XBus (is a packet switched version of MBus used with SPARC-architecture CPUs, Sun Microsystems. XBus ran at 40MHz and is OBSOLETE.)
XGMII Bus {10 Gigabit Media Independent Interface [XGMII]. XGMII supports full duplex operation only. All signals use the HSTL_I bus standard; this is a general-purpose high-speed 1.5 V standard, requiring a differential amplifier at the input and a push-pull driver on the output. The XGMII tracks are only designed to be a few centimeters in length (approximately 7cm). Uses SSTL_2 interface levels. provides an optional interconnection between the Media Access Control (MAC) sublayer and the Physical layer (PHY) of 10 Gigabit Ethernet.}
XIO (An interface used on some SGI computers to interface between ASIC processors and memory controllers, in the mid 2000's}
XSBI Bus (10-Gb Sixteen Bit Interface [XSBI], the 'X' stands for 10. Interfaces ICs and optical transponders under 10 Gigabit Ethernet.}
ZWD {Zero Wire Debug, A non existent bus [in research] that uses coils inside an IC to inductively couple [test signals] to a wireless probe [flex cable with it's own coils] which than communicates with the debugger. So the IC does not need to devote any external pins to a debug bus as they are inductively coupled to the probe via the embedded coil. Proposed nets include; Tx, Rx, and Clk. }
All of the different interface bus descriptions or links to electronic bus pages listed above deal with layer 1 [Physical, Electrical and Mechanical Layer] of the OSI protocol stack. Many electronic bus pages also reference layer 2; the Data Link Layer [which provide bit/byte stuffing, checksum, Protocols..]. In addition, all of the page links listed above provide links to devices related to that particular bus, which include IC manufacturers, Connector manufacturers, Bus Termination manufacturers, cable manufacturers, and electronic equipment manufacturers, Standards/Specifications and so on... The extent of the description provided for any particular electronic bus varies widely from page to page depending on the bus.
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