SOC Bus Description

SOC [Systems-On-Chip] buses are not real physical buses.
SOC buses reside within an FPGA and are used to interconnect an IP core to the surrounding interface logic.
A SOC bus provides a way to define an IP core with I/O and allow an interconnection method to the core.
With out a predefined bus, the interface would need to be redesigned for each IP core used.
SOC have a few different names and may also be seen as;
SOPCs: systems on re-programmable chips
CSoC: configurable SoC
NoC; Network-on-Chip
PSoC: Programmable System-on-Chip
PPSoC: Power Programmable System-on-Chip.

IP: "Intellectual Property",.
IP cores are pre-designed modules used in FPGAs, PLDs, or ASICs.
The IP buses are used to interconnect the modules [or Blocks] within the core and or user defined logic within the gate-array.
These designs are also called Systems-On-Chip [SOC].
There are many IP buses, a few Open Source ones are listed here. IP Cores are listed on their own page.
Of course almost any predefined bus may also be integrated onto an IP core; a few common ones are: I2C, USB, CAN, and JTAG.
These should not to be confused with the mezzanine IndustryPack "IP" standard, which is a board standard.

IP Core Buses

Atlantic Interface Altera Corporation

Avalon Bus Specification Altera Corporation ......

Wishbone
{Wishbone is a public domain document and is available at no cost. Products may use this standard without any royalty obligations}. The Wishbone specification is now controlled by OpenCores.org. The Wishbone IP core bus was developed to interconnect IP cores within an FPGA and does not support external buses. The Wishbone developer site had provided VHDL code, but that site has been off-line for months. The specification is always available by the link provided above. The Wishbone standard allows IP core interconnection, but the VHDL code may have to be developed as needed. The Full title: WISHBONE System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores

ARM Ltd Developed the AMBA specification which my be comprised of;
AHB: [Advanced High-performance Bus],
APB: [Advanced Peripheral Bus],
ASB :[Advanced System Bus]

{AMBA is an open standard, on-chip bus specification}. AHB-Lite is a subset of the full AHB specification and is used with a single bus master. Multi-layer AHB info TBD...

AMBA Rev 2.0 [www.arm.com]......
The Full title: Advanced Microcontroller Bus Architecture [AMBA]
Free of any charges. Available under a simple license agreement

Aurora is an open protocol specification offered by Xilinx [free of charge], under a simple license agreement.
Aurora is a scalable, link-layer protocol that is used to move data across point-to-point serial links. The Aurora specification defines both the IP Core interface, and an external FPGA [LVDS] interface, in addition to the interconnect protocol. The 1x Aurora interface consists of 1 set of differential driving pairs and 1 set of differential receiver pairs [3.125Gbps RocketIO serial transceivers]. RocketIO is a Xilinx term.

Aurora offers unlimited bonded lanes for high aggregate bandwidth [baud rate of up to 75 Gbps]. Aurora can aggregate 1 to 24 physical lanes together into a single logical channel. The Aurora interface [Protocol] supports Full Duplex & Simplex channels, using either 8B/10B or 64B/66B encoding schemes. The [Differential] LVDS will support Chip-to-Chip, Board-to-Board [backplane or Cable] and Box-to-Box interfacing. The embedded Aurora interface [and it's interface speed] is optimized for Xilinx IP cores and is available for down-load, non-Xilinx cores may not obtain the stated bus speed. Also see VITA 55 Aurora; standard for Aurora on VITA 41, 42, and 46 form factors

CoreConnect Bus [IBM]. No-fee, no-royalty licensing. Just apply for a license over the web.

Open Core Protocol 'OCP' Open Core Protocol International Partnership (OCP-IP)
{OCP is available at no cost, under License agreement that is agreed to over the web. Products may use this standard without any royalty obligations}. How ever I believe you have to be a member of OCP, which will incur a cost.

STBus is STMicroelectronics best solution for interconnecting IPs, of any data width, clock frequency and complexity, in a system-on-chip. Can be interfaced to APB/AHB/AXI IP Cores and peripherals

ST Network on Chip [NoC], another Soc Bus from STMicroelectronics. May also be found as STNoC.

EIB [Element Interconnect Bus] is a communication bus internal to the Cell processor which connects the various on-chip system elements:
the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants.
The EIB also includes an arbitration unit which functions as a set of traffic lights.

The EIB is presently implemented as a circular ring comprised of four 16B-wide unidirectional channels which counter-rotate in pairs.
When traffic patterns permit, each channel can convey up to three transactions concurrently.

Additional Topics

IP Core Manufacturers Listing

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