HSSTP Description

The High Speed Serial Trace Port [HSSTP] specification uses the connector defined in the HSSTP specification, the Aurora protocol developed by Xilinx and the electrical interface defined by XAUI. Refer to the main HSSTP page covering the standard.

Four dual-row connector sizes are allowed; 22-pins, 34-pins, 46-pins and 70-pins. The HST-34 connector [covered here], provides four differential transmit pairs and 2 differential receive pairs, a Vsense line, five JTAG pins, six Vendor I/O pins, a Reset line and an optional differential clock line.
Ground pins are also supplied per differential pair, which are longer and mate first.
The Vendor I/O pins are SoC specific and are not defined in the HSSTP specification.
The pinout variations are provided below, shown by number of pins.

HSSTP Pinouts

HSSTP Connector Pinout Variants

Simplex 11 x 2 HSSTP, 4 differential TX lines.
Simplex 17 x 2 HSSTP, 6 differential TX lines.
Simplex 23 x 2 HSSTP, 8 differential TX lines.
Duplex 11 x 2 HSSTP, 2 differential TX lines, 2 differential RX lines.
Duplex 17 x 2 HSSTP, 4 differential TX lines, 2 differential RX lines.
Duplex 23 x 2 HSSTP, 4 differential TX lines, 4 differential RX lines.
Duplex 35 x 2 HSSTP, 8 differential TX lines, 4 differential RX lines.

The latches are used to secure the connector and are not pins.