HSSTP Description

The High Speed Serial Trace Port [HSSTP] specification uses the connector defined in the HSSTP specification, the Aurora protocol developed by Xilinx and the electrical interface defined by XAUI. Refer to the main HSSTP page covering the standard.

Four dual-row connector sizes are allowed; 22-pins, 34-pins, 46-pins and 70-pins. The smallest connector, 11x2 [covered here], provides four differential transmit pairs, a Vsense line, five JTAG pins, four Vendor I/O pins and a Reset line.
Ground pins are also supplied per differential pair, which are longer and mate first.
The Vendor I/O pins are SoC specific and are not defined with the HSSTP specification.
The 4 vendor lines are optional and need not be driven.
The pinout variations are provided below, shown by number of pins.

HSSTP Pinouts

Simplex HST-S22
11 x 2
Pin NumSignal name Signal namePin Num
LatchGND GNDLatch
1TX0+ VIO (Vsense)2
3TX0- TCK4
7TX1+ TDI8
9TX1- TDO10
13TX2+ Vendor I/O 014
15TX2- Vendor I/O 116
17GND Vendor I/O 218
19TX3+ Vendor I/O 320
21TX3- Reset22
LatchGND GNDLatch

HSSTP Connector Pinout Variants

As shown more lanes are added as the connector size increases.
Larger connectors add more Transmit and or Receive pairs.
Although some pin pairs are reserved on the larger connectors.
Simplex 11 x 2 HSSTP, 4 differential TX lines. Covered Here.
Simplex 17 x 2 HSSTP, 6 differential TX lines.
Simplex 23 x 2 HSSTP, 8 differential TX lines.
Duplex 11 x 2 HSSTP, 2 differential TX lines, 2 differential RX lines.
Duplex 17 x 2 HSSTP, 4 differential TX lines, 2 differential RX lines.
Duplex 23 x 2 HSSTP, 4 differential TX lines, 4 differential RX lines.
Duplex 35 x 2 HSSTP, 8 differential TX lines, 4 differential RX lines.

The latches are used to secure the connector and are not pins.
The latch is a mechanical clip on each end of the connector.

Simplex Operation
HST-S22 Size
Transmit Only

PC motherboard

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Modified 1/15/12
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