General Engineering Terms
"A" "B" "C", "D", "E", "F", "G", "H", "I", "J", "K", "L", "M",
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## Trapezoidal Generator

A trapezoidal signal has two parallel sides, with four sides total. In this case the two parallel sides are the rising and falling edges of the waveform. The other two sides are the top and bottom of the wave form. The bottom of the waveform is of course the base voltage.

The circuit presented here is used to generate a Trapezoidal waveform. This particular circuit is not an oscillator but a converter which transforms an input trigger signal into an output that has a trapezoid wave shape. A transistor is used in this circuit example, but many other circuit configurations could be used.

 The circuit to the right is a standard common emitter transistor amplifier. The input signal is applied to the Base of the transistor, and the output is taken from the Collector of the transistor. The Emitter leg is grounded or common to both the input circuit and output circuit. Trapezoidal Circuit

The shape of the top of the pulse is normalized, but is really based on the RC rise time of the voltage across a capacitor [which may not be linear as shown]. However depending on the frequency of the signal and the time base of the oscilloscope it may appear very linear. Again, the voltage across a charging capacitor follows a predictable formula and is not linear, so it's important to use the portion of the Rise Time that is most linear. The longer a capacitor is allowed to charge the less linear the charging voltage becomes. So the input voltage which controls the charging of the capacitor needs to be configured to only allow the capacitor to charge to a small portion of the maximum voltage, below one time constant [1TC] as seen in the graph below.

The input signal frequency needs to be selected so that the output has the desired output frequency. The frequency that the transistor turns on and off is determined in part by the frequency of the input signal. Assuming that the input signal is periodic, the frequency of the input directly controls the frequency of the output waveform.

### Transistor Operation

The circuit is configured as a standard Common-Emitter amplifier. Capacitor C1 is a DC blocking capacitor and blocks any DC bias voltage from a previous stage from reaching this circuit. The values of C1 should be selected so it offers no resistance to the input signal, but only blocks direct current. So the value should be scaled to a lower value as the input frequency is increased to offer a low impedance to the incoming frequency. The rise and fall time of the input may also be an important component of the signal frequency.

Resistor R1 is a bias resistor [Rb] which fixes the Base voltage at Vcc when no input signal is applied, and used to select the Base current [Ib] for the transistor. The Base current is provided in the transistor data sheet, as well as the Base Emitter voltage Vbe. The resistor R1 is then equal to [Vcc -Vbe] / Ib. Resistor R2 is the collector bias voltage which sets the collector voltage at Vcc and the collector current to Vcc/R2. Resistor R3 and Capacitor C2 form the output or load circuit and are used to generate the linear slope of the output signal [the slope of the pulse top].

The transistor Q1 may be any NPN device, and should be selected based on the requirements of the circuit. Data for a number of transistors are provided on the site, including the 2N2222 Transistor in a TO-18 Package. Another common substitute for a general purpose transistor would be the 2N3904 NPN transistor.

The transistor is biased on by the Base resistor R1, and Base current flows from Vcc through R1 into the base of the transistor and out to ground through the Emitter leg. The transistor is turned on and Collector current flows through the collector emitter junction. The collector is grounded and the voltage at the node between resistors R2 and R3 is zero. The voltage across the timing capacitor is also zero, or very quickly zero as the capacitor discharges through Q1.

As an external input is applied to the Base of the transistor, base current is reduced leading to a reduction of collector current. As the input voltage is made more negative until the Base current falls to zero, reducing the output current to zero and turning off the transistor. The transistor turns on and off based on the input voltage

So the output basically turns on and off following the trigger pulse of the input. The difference is that part of the output is a function of the voltage across the capacitor C2. Without the capacitor the output would either be zero when the transistor is full on or the result of the resistor divider formed by R2 and R3 [Vcc * R3/(R2 + R3)]. If the input is a narrow pulse, the output would follow with a narrow pulse, switching from 0 volts to Vcc.

When the transistor is tuned on the output voltage falls to zero based on the discharge rate of the resistor / capacitor combination [RC]. For this example the discharge rate is; 5k x 0.02uF, or 100uS. Decreasing the value of either R3 or C2 will cause the fall time to decrease, while increasing either value will produce a longer fall time. The input is assumed to either fully turn or of fully turn off the transistor, but a slow change at the input will also slow the fall time.

When the transistor is shut off, the output is initially produced by the resistor divider network [the Jump voltage in the diagram]. So the initial voltage step is controlled by R2 and R3. However an increasing voltage ramp [linear slop in the diagram] is produced by the capacitor charging up to Vcc. The final level of the output is controlled by the either the capacitor reaching Vcc, or the input pulse turning the transistor back on and forcing the capacitor to discharge.

The capacitor should only be allowed to charge 39 percent of Vcc, otherwise the charging becomes non-linear. So the input frequency, or duty cycle needs to be control to turn the transistor on before half a time constant. R2 needs to be adjusted to change the time constant [RC], or the value of the capacitor needs to be adjusted. The charging time of the capacitor is based on (R2 + R3) * C2, or R2 * C2 [Vcc through the RC network to ground]. While the much faster discharge rate is controlled by R3 * C2 [through the transistor collector].