2N6301 Temperature-Power Derating Curve [2N6301]
NPN Medium Power Switching Transistor. Package, TO-66 metal Can.
2N6301 Derating Graph, Maximum Operation
Use the Graph to determine how much to derate power [wattage] based on operational case temperature [in still air]. Used forced air via a fan to achieve higher operational temperatures or power dissipation [Fan Manufacturers].
The above chart details the maximum allowable power dissipation with increasing ambient temperature. Maximum operational power dissipation is achievable at 250C. However above 25C the maximum package dissipation, or power, must be reduce to insure that the devices junction temperature remains constant. The higher the ambient temperature is increased the lower the allowable power dissipation, as depicted in the curves.
Derating Equation; Derate linearly 0.428 W/0C above Tc > 250C
Decreasing a devices operational limits as temperature is increased is called derating, in this case derating a devices operational power dissipation vs increasing ambient temperature.
Refer to MIL-PRF-19500/539; [TO-66] Semiconductor Device, Transistor, NPN, Silicon Power, Types 2N6300 and 2N6301, JAN, JANTX, and JANTXV
Case mount. [Flange Mount] A type of package which provides a method of readily attaching one surface of the
semiconductor device to a heat dissipater [Heat Sink] to achieve thermal management of the case temperature (example: TO-66). The Collector of this device is directly connected to the case or body of the metal package.
[BJT Derating Definitions, near bottom of page]
2N6301 Schematic Circuit
Safe Operating Area
Collector Current vs. Collector-Emitter Voltage.
The graph to the left provides the Maximum Safe Operating Area for the 2N6300 and 2N6301 Transistor. The curves happen to be almost identical until the collector current drops below 1 amp.
Other than a difference in collector to emitter voltage the 2N6300 is about the same as the 2N6301 transistor. The 2N6300 uses a 60V dc Veco, while the 2N6301 will handle 80 volts. Note that this is also the difference in the termination point of the two transistors shown in the chart.
