"A",
"B",
"C",
"D",
"E",
"F",
"G",
"H",
"I",
"J",
"K",
"L",
"M",
"N",
"O",
"P",
"Q",
"R",
"S",
"T",
"U",
"V",
"W",
"X",
"Y",
"Z"
Memory Module Definitions
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Description of Memory Module Types
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DDR:
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Double Data Rate [Data moves which each edge of the clock]
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DDR2:
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Double Data Rate
NOTE [On-Die-Termination, ODT, Architecture Changes]
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DDR3:
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Double Data Rate, third generation
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DDR-FCRAM:
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Double-Data-Rate, Fast-Cycle Random Access Memory [Different core
memory arrangement then DDR RAM]
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DIMM:
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Dual In-Line Memory Module. The front side PWB pins
are not connected to the rear side pins, pins used for different
functions.
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DRAM:
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Dynamic Random Access Memory (Requires Refresh)
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DRSL:
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Differential Rambus Signaling Levels
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FB-DIMM:
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Fully-Buffered DIMM [utilizes JEDEC-standard DDR2 SDRAM]
|
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GDDR:
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Graphics DDR I/II/III/IV; GDDR1, GDDR2, GDDR3, GDDR4 -
1.25GHz Clock for GDDR4
|
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PSRAM
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pseudo-SRAM
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QBM2
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Quad Band Memory, DDR Compatible at increased speed
|
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QDRII:
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Quad Data Rate [also called DDR2, DDRII, QDRSRAM, and QDR-2 SRAM]
|
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RDIMM
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Registered DIMM
|
|
RIMM
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Rambus DIMM [RDRAM], In-stalled in pairs. 16-bit modules are 184-pin
or 32-bit modules at 232-pins
|
|
SDR DRAM:
|
Single Data Rate SDRAM
|
|
SIMM:
|
Single In-Line Memory Module. Data width is 32 bits
per memory stick, the front 72 pins and back 72 fingers on the card
are connected together. While DIMM pins are not.
|
|
SODIMM:
|
Small Outline Dual In-Line Memory Module [used in Laptops / Notebooks]
|
|
SOCDIMM:
|
Small-Outline Clocked DIMM, ultra-narrow SODIMM form factor
|
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SORDIMM:
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Small-Outline Registered DIMM, ultra-narrow SODIMM
|
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SRAM:
|
Static Memory; Faster than DRAM, but more expensive
|
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UDIMM
|
UnBuffered DIMM
|
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ULP-DIMM
|
Ultra Low Profile DIMM [small form factor DDR/DDR2 Server/Routers/Switch memory]
|
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VLP-DIMM
|
Very Low Profile DIMM [small form factor DDR/DDR2 Server/Routers/Switch memory]
|
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XDR:
|
Memory sticks using DRSL [also called XDIMM], Memory type from RAMbus
|
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XDR2:
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Memory type from RAMbus
|
|
ZB-DDR:
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Zero-Buffer DDR
|
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HDIMM
|
....
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Definition of Memory Module Terms
|
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CAS Latency:
|
Column Access Strobe, is the relationship between
Column Access Time and Clock Cycle Time.
|
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CAS-2:
|
wait 2 clock cycles after the Column Address before
the data appears. CAS-3, wait 3 clock cycles.
|
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ECC:
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Error Correcting Code, an additional 8 bits [to 64-bit
data] of ECC for a total of 72-bits [72-bit wide data]
|
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Bank
|
The DRAMs on a module are organized into a number of
Banks that can be accessed simultaneously.
|
|
Rank
|
Defines a set of DRAM chips (on a module) comprising 8
byte wide (64 bits) data, or 9 bytes (72 bits) with ECC. All devices
in a Rank are connected by a single Chip-Select. The actual memory
size is not defined. Single-sided memory modules are always
Single-Rank. Double-sided unbuffered DIMMs and SODIMMs are always
Dual-Rank. Server DIMMs may have up to 4 ranks.
|
|
Dual Rank
|
Defines 2 sets of DRAM chips (on a module) each
comprised of 8 byte wide (64 bits) data, or 9 bytes (72 bits) with
ECC. All devices in a Rank are connected by a single Chip-Select. The
actual memory size is not defined. Normally a module will have one
rank per PWB side.
|
|
Quad Rank
|
Defines 4 sets of DRAM chips (on a module) each
comprised of 8 byte wide (64 bits) data, or 9 bytes (72 bits) with
ECC. All devices in a Rank are connected by a single Chip-Select. The
actual memory size is not defined. Normally a module will have two
ranks per PWB side.
|
|
Registered DIMM
|
Buffers the Address and Clock signals on each DIMM to
enhance the signal quality.
|
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SO:
|
Small Outline (Memory Module), as in SO-DIMM
|
