I2C Bus {Inter-IC [I2C, IIC] Designed as a battery control interface, now used in microcontroller-based [uP] professional, consumer and telecommunications control, diagnostic and power management buses. The I²C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. 3 speed modes are specified: Standard; 100kbps [Bits per Second], Fast mode; 400kbps, High speed mode 3.4Mbps.}

I₂O Bus (Intelligent Input/Output [or Intelligent I/O] Bus was designed to eliminate I/O bottlenecks by utilizing special I/O processors [IOPs] to off-load work. It was more a Software driver architecture spec then hardware bus. The specification was released in 1997, looks like work on the spec stopped in 2000. Also called IIO Bus.)

I²S Bus (Inter-IC Sound [I2S, IIC] is a serial bus designed for digital audio devices. The I2S design handles audio data separately from clock signals. An I2S bus design consists of three serial bus lines: a line with two time-division multiplexing (TDM) data channels, a word select line, and a clock line. The I2S bus turns up on DAC's or micro-processors.)

IBA Bus {Intermediate Bus Architecture. Voltage regulator to any regulator}

ICMB {Intelligent Chassis Management Bus, is a supporting document to IPMI}

IDE Bus {IDE, ATA or PATA, Internal parallel Bus used as a Personal Computer Hard-Drive interface. The maximum bus speed is 133MBps over an 18 inch Parallel cable.}

iDP Specification {Internal DisplayPort}

IEBus {Inter Equipment Bus is used as In-vehicle bus using half duplex asynchronous [Multi-Master] communication with CSMA/CD for access control. Two differential lines are used; Data+ / Data-. Two modes are defined: Mode 0 uses 16 bytes/frame and runs at 3.9kbps or 4.1kbps. Mode 1 uses 32 bytes/frame and runs at 17kbps [6MHz Osc.] or 18kbps [6.29MHz Osc.]. The IEbus allows 50 units on the bus up to 50 meters.}

IEEE-488 {Digital Interface for Programmable Instrumentation, HPIB, GPIB.}

IEEE-696 {S-100 bus, Obsolete}

IEEE-1174 { [Serial Interface for Programmable Instrumentation] is basically IEEE-488 over an RS-232 link. IEEE-1174.0 defines the electrical and mechanical implementation over RS-232. IEEE-1174.1 defines ports GPIB onto the serial interface. IEEE-1174.2 details the functionality and implementation of the required IEEE-488.2 over the serial link [EIA/TIA-574]. }

IEEE-1284 {Personal Computer parallel Bus. [Copper wire interface]. Used as a Bi-Directional Parallel Peripheral Interface, mainly used as a Printer Bus for PCs. The maximum printer cable length is 25 feet. The Centronics parallel cables run to 12 feet.}

IEEE-1355 (The HIC bus is a bidirectional serial interconnect which builds a scalable parallel system using a pair(s) of unidirectional lines.)

IEEE 1394 Bus {Bus Standard using CAT5 cable allows 100Mbps data to travel 100m}

IEEE-1596 {SCI (Scalable Coherent Interface). SCI is a scalable network, nodes are interconnected in a point-to-point unidirectional link [ring]. The bandwidth grows with the number [concurrent] nodes used. SCI links are operate at 1 Gbps [serial], or 1 GBps [16-bit parallel], using a 250-MHz bi-phase clock over fiberoptic or twisted-pair wires. Physical SCI controllers use LVDS signaling levels for 16 and 8 bit wide links.}

iLink {Sony's name for FireWire, i.Link is based on IEEE-1394 using metallic conductors.}

Industrial Board Formats {Links and Board sizes}

IndustrialPCI Bus

Industrial PCI Express {[IPCI-E], PICMG 1.3 adds PCI Express to the PCI-ISA Passive Backplane Specification.}

InfiniBand bus (Bi-direction differential LVDS wire pairs, over fiber or copper cable.)

InterBus (Field Bus)

Inter Chip USB (The USB standard for Chip-to-Chip interconnects)

IPMB (Intelligent Platform Management Bus)

IPMI (Intelligent Platform Management Interface)

IP / SoC Core Buses {Intellectual Property [IP] or System-On-Chip [SoC] Bus connects pre-designed modules [IP's] used in FPGAs, PLDs, or ASICs}

IRDA Bus {IRDA -Information-IC/Connector Links}

ISA/AT Bus {8MHz @ 8 and 16 bits data bus, 24 bit address bus, +/- 12v, +/- 5 volts, 15 Interrupt lines. The AT card used the standard edge connector provided by the XT bus with an additional edge connector behind that with the same pin-spacing, 0.1 inch center-to-center. The additional connector has only 38 (19 per side) fingers, while the XT connector had 62 (32 per side) fingers. The Mother Board could then accept either an 8 or 16 bit card in an 8 bit slot (XT), or a 16 bit card in an AT slot. The PCI bus replaced the PCAT.}

ISA/XT Bus {Obsolete; 4.77MHz, 8 bits, +/- 12 volts, +/- 5 volts. The XT bus used a 62 pin (.1" center) edge connector; 31 pins per card side. 8 Data lines, 20 Address lines, 1 Clock 4.77MHz line. 1 Reset line, 8 Interrupt lines. Some 8 bit cards have skirts which extend the board below the depth of the top of the connector to allow additional circuitry. CCA skirts are not compatible with the 16 bit AT bus. The XT bus uses connector J1 (A/B), AT uses J1 (A/B), J2 (C/D).}

iSCSI {Internet SCSI; sending SCSI commands over IP networks}

ISDN Bus {Integrated Services Digital Network, xDSL}

An alphabetic listing of released interface buses. Primarily the links point to pages that describe the physical and electrical interfaces. Interface Bus protocols are not addressed.