Electronic Engineering Dictionary

IC Clock Buffer Chips

1-to-10 Clock Buffer Chip

Pulse-to-Pulse skew is the important characteristic. Each output should switch, as close as possible, soon after the first output switches. The IC is designed so that all the outputs change within a very small window. Otherwise the clock buffer would not serve its purpose, the single clock pulse would arrive at 10 different destinations at completely different times. The propagation delay between the input changing and the output changing is given by Tpd. The propagation is given for each output and changes slightly. The over-all propagation difference between the outputs is given by the timing skew; Tsk. The timing skew is the characteristic to control, as seen in the timing diagram to the right.

IC 1-Line to 10-Line Clock Buffer Chip. Clock Distribution. The purpose of a clock buffer is to transmit or fanout the clock to multiple ICs at the same time. To accomplice this the clock buffer has a very small timing skew from driver to driver so the clock arrives at each of the destination ICs all at the same time.

Clock Buffer by Function:
CDC2351: Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation.
The output-enable (OE) input disables the outputs to a high-impedance state.
The propagation delays are adjusted at the factory using the P0 and P1 pins. Pins P0 and P1 are not intended for customer use and should be connected to GND.

There are many different types of clock drivers or clock buffers, some with only two outputs. An IC with one output would just be a buffer chip, although there are one bit clock driver ICs [perhaps with a fixed, predictable propagation delay]. The point of these clock buffers are to drive the same clock to a number of inputs all changing levels at the same time, so all the receives see the clock at the same time.

Clock Distribution; Clock Buffer Vendors.

Logic Design; IC Propagation delay, and IC Fanout.