Element Interconnect Bus Description

Element Interconnect Bus

The Element Interconnect Bus [EIB] is a communication bus internal to the Cell processor which connects the various on-chip system elements:
the PPE processor, the memory controller (MIC), the eight SPE coprocessors, and two off-chip I/O interfaces, for a total of 12 participants.
The EIB also includes an arbitration unit which functions as a set of traffic lights.

In some documents IBM refers to EIB bus participants as 'units'.

The EIB is presently implemented as a circular ring comprised of four 16B-wide unidirectional channels which counter-rotate in pairs.
When traffic patterns permit, each channel can convey up to three transactions concurrently.
As the EIB runs at half the system clock rate the effective channel rate is 16 bytes every two system clocks.
At maximum concurrency, with three active transactions on each of the four rings,
the peak instantaneous EIB bandwidth is 96B per clock (12 concurrent transactions * 16 bytes wide / 2 system clocks per transfer).
While this figure is often quoted in IBM literature it is unrealistic to simply scale this number by processor clock speed.
The arbitration unit imposes additional constraints which are discussed in the Bandwidth Assessment section below.

Note: I left this snippet in my to-do list for so long I no longer remember if I wrote this or copied it as a reference artical .....

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