VME/VXI Timing Diagrams

VXI Data Bus Transfer Timing

VXI Data Transfer Timing

The Master places data on the Data Transfer Bus, then waits a minimum of 35nS before bringing one or both of the Data Strobe(s) low. The Data Strobes going low indicate to the Slave that the Master has placed valid data on the bus. There is no defined time for the Slave to acquire the data and acknowledge the transfer. Once the Slave has latched the data it will bring DTACK low. The Master will then release the Data Strobe(s). Once both of the data strobes are taken high the slave will release DTACK completing the data transfer cycle.

VXI Address Transfer Timing
All Extracted from -- Interface Board VME Design 1/03/93, Leroy Davis

The Master takes IACK high and places the address and AM codes on the bus. Once the lines have been valid for 35nS the Master takes the Address Strobe [AS] low to indicate a valid address on the bus. For Interrupt cycles the IACK lines are driven low

VXI Timing Diagrams; TTL / ECL Triggers

Back to the main VXIbus section.

Engineering Key Words: VXI, VME, VMEbus, Bus, Interface, Control, Signals, Timing
Data Timing Diagram, Address Timing Diagram.


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