How to read these Transistor Temperature-Power Derating Curves

2N2904 Temperature-Power Derating Curve
2N2904 Transistor Temperature-Power Derating Curve

The chart details the maximum allowable power dissipation with increasing ambient temperature. Maximum operational power dissipation is achievable at 25C. However above 25C the maximum package dissipation, or power, must be reduce to insure that the devices junction temperature remains constant. The higher the ambient temperature is increased the lower the allowable power dissipation, as depicted in the curves.
The graph above depicts the derating of a 2N2904 transistor in a TO-39 package.

Decreasing a devices operational limits as temperature is increased is called derating, in this case derating a devices operational power dissipation vs increasing ambient [surrounding] temperature.

The derating chart is made up of a number of curves.
The top most curve [dashed line] is thermal run-away and cannot be used as a derate design curve since it exceeds the maximum ratings for the 2N2904. Operating under this curve using these mounting conditions assures the device will not have a thermal runaway.

The next curve [solid line] represents the 2N2904 operating at its maximum junction temperature [Tj]. In truth no derating has occurred by using this curve, as the device is being operated at its maximum limit of 200C.

The curve that terminates a 150C is a possible operating limit and represents a reduction of 50C from the max junction temperature. However this curve is really presented to show the junction temperature that the electrical tests are performed at.

The final two curves terminating at a Tj of 125C and 110C represent the junction temperature that most circuits should be designed to operate at. Of course operating at the lowest junction temperature will result in the longest life of the device, translating into higher reliability.

The flat portion of the curve at 0.8 watts depicts an absolute maximum rating regardless of temperature. For a 2N2904, this could be due to wirebond limitations or gain roll-off.
The second flat region at 200C where the curve suddenly truncates depicts a physical package limitation; in this case, the lead solder dip. Other package limitations could include lid braze preform melt temperature.

Recall that this graph was developed using still air with no other near-by components. Placing the 2N2904 inside a case which limits air flow, or placing it next to other heat generating components will cause the 2N2904's temperature to increase. Add forced air to over come these constrains.

Case temperature. The temperature measured at a specified point on the case of a semiconductor device.

How to Derate; Guideline for Derating Electronic Components

Department of Defense Specifications:
MIL-PRF-19500; Semiconductor Devices, General Specification

Department of Defense Standards:
MIL-STD-750; Test Methods for Semiconductor Devices

Google
TO-254 Package dimension Drawing
TO-254AA Package

Complete list of
NPN Transistor Derating Curves.

Complete Listing of
Transistor Manufacturers, BJT vendors.

TO-3 Package
TO-3 Metal Can

Engineering Key Words:
Transistor, Component Derating, reliability,
Sizing, Derate, Semiconductor, 2N6249,
Insulation, Rated Temp, Temperature,
Guide, How To, Guideline, Example,
Burn-Out, Design, Failure, MTBF, NPN.

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Last Modified 11/27/09
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