Serial RapidIO Bus

Serial RapidIO Description

sRIO is a point-to-point, packet-switched interconnect technology implementing LVDS as the electrical interface.
Serial RapidIO is the serial implementation of the RapidIO interface over a serial physical layer.
Of course both the serial and parallel RapidIO interfaces use serial links, the difference is the number of links.
Serial RapidIO is the reduced pin count of RapidIO, and the electrical interfaces are identical.
Clock and data are embedded on the same data stream using 8B10B encoding.
Each serial differential pair is called a lane, Serial RapidIO uses either 1 lane or four lanes [1x/4x].
Other than the difference in the number of lanes, its basically the same as parallel RapidIO.

LVDS Ponit-to-Point Electrical Interface
LVDS Single Link Interface Circuit

An LVDS interface is a single differential link in either one or both directions.
Each link requires a termination resistor at the far [receiver] end.
The nominal resistor values used is 100 ohms, but depends on the cable or PWB trace impedance.
RapidIO signal traces should be 100 Ohm differential impedance, with Terminations to match.
Normal high-speed routing rules apply, the same as any differential pair.
Terms and definitions used with board layout and PCB Topics.

Switched Fabric Standards and Specifications Info

RapidIO Trade Association []

RapidIO Specification 1.3 [released in 2005]
RapidIO Specification 2.1 [released in 2008]
Part 6: Serial Physical Layer Specification

EIA-644 description, the spec that defines LVDS.
Or at least one particular version of a low voltage differential interface.

sRIO Interface IC Manufacturers

IC may be found as LVDS or LpLVDS [Low power] which are interoperable.
LpLVDS does have a reduced voltage swing (250mV) and slower edge rates.

IDT {Pre-Processing Switch}

PMC-Sierra, Inc.

Texas Instruments

Related topic for high-speed interfaces; Calculating Propagation Delay in a system.

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Modified 1/25/12
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