SSTL [Stub Series Terminated Logic] is an electrical interface
commonly used with DDR [Double Data Rate] DRAM memory ICs and memory modules.
There
are a number of standards that define SSTL levels for ICs and or memory
module, a few are listed below under the standards section; however there
may be revisions or addendums not listed.
There are currently three main
types of SSTL signally standards.
These include the switching levels for SSTL_3, SSTL_2, and SSTL_18, which are each defined by a different JEDEC
document number.
SSTL_18 Series Stub Terminated, used with DDR II memory; requires
Vddq = 1.8v, Vt = 0.5 x Vddq
SSTL_2 Series Stub Terminated, used with DDR I memory; requires
Vddq = 2.5v, Vt = 0.5 x Vddq
SSTL_2 interconnects require a 25 ohm series resistor at the source and a
50 ohm termination resistor at the destination pulled to Vtt [assuming a
50 ohm class I system].
Set the termination resistor to 25 ohms in a
class II to system [class II uses 16.2mA, class I use 8.1mA].
Bi-Directional signals require the 50 termination resistor at the source
in additional to the series termination resistor.
SSTL-2 is defined by the JESD8-9 specification.
SSTL_3 Series Stub Terminated, used with DDR memory; requires Vddq = 3.3v, Vt = 0.5 x Vddq
JESD8-9 Stub Series Terminated Logic for 2.5 Volts (SSTL_2)
JESD8-15 Stub Series Terminated Logic for 1.8 Volts
(SSTL_18)
JESD 79-2A DDR2 SDRAM Specification
JESD 82-13A Definition of the SSTVN16859 2.5-2.6 V 13-BIT TO
26-BIT SSTL_2 Registered Buffer for PC1600, PC2100, PC2700 AND PC3200 DDR
DIMM Application
JESD 82-3B Definition of the SSTV16857 2.5 V, 14-BIT SSTL_2
Registered Buffer for DDR DIMM Applications
JESD 8-15A Stub Series Terminated Logic for 1.8 V (SSTL_18):
Switching from 0v to 1.8 volts.
The following classes are defined by standard JESD8-6 from JEDEC:
Class I (unterminated, or symmetrically parallel terminated)
Class II (series terminated)
Class III (asymmetrically parallel terminated)
Class IV (asymmetrically double parallel terminated)
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