System Packet Interface Level 4
The Packet Over SONET Physical Layer Level 4 (POS-PHY L4) interface defines the interconnection of Physical Layer devices to Link Layer devices in POS applications. The interface cores, referred to as SPI-4 cores, perform the interface functions on the Physical Layer or Link Layer side of the interface.
The standard is: System Packet Interface Level 4 (SPI-4) Phase 2 Revision 1: OC-192 System Interface for Physical and Link Layer Devices.
Cortina Systems, Inc. {SPI4.2 uplink interface w/ many line interface solutions}
Exar {OC-48 ETHERNET/SONET MULTI-SERVICE FRAMER PROCESSOR}
IDT {SPI-3 to SPI-4 packet-exchange devices}
PMC-Sierra {STS-48c/STM-16-16c ATM & POS Phy with Utopia Level 3, POS-PHY Level 3/SPI-3 & PECL}
Rambus {SPI-4.2 Multi-channel Controller}
Xilinx {FPGA Cores, and Interfaces}
SPI3 Description and SPI3 Devices
Engineering Design Key words: SPI4, Optical Transport Network, OTN, SONET Bus, SDH, Synchronous Optical NETwork, Electrical Standard, Interface Standard, Specification, Spec, Fiber, Electrical Interface, Data Rate, IC Semiconductor manufacturers, Physical Interface, Engineering Description, electrical characteristics, Component Manufacturers, Optical Carrier, Line-Terminating Equipment, LTE, Path-Terminating Equipment, PTE
|
|
|||||||
| Home | |||||||
|
|
|||||||
|
|
|
|
|
|
|
|
|
| Distributors | Components | Equipment | Software | Standards | Buses | Design | Reference |