System Packet Interface Level 3
The Packet Over SONET Physical Layer Level 3 (POS-PHY L3) interface defines the interconnection of Physical Layer devices to Link Layer devices in POS applications. The interface cores, referred to as SPI-3 cores, perform the interface functions on the Physical Layer or Link Layer side of the interface.
The standard is: System Packet Interface Level 3: OC-48 System Interface for Physical and Link Layer Devices
Cortina Systems {Octal OC-48/12/3 Framer / GE MAC, OC-48 ATM SAR / TM with SPI-4.2}
Exar {OC-48 ETHERNET/SONET MULTI-SERVICE FRAMER PROCESSOR}
IDT {SPI-3 to SPI-4 packet-exchange devices}
PMC-Sierra {STS-48c/STM-16-16c ATM & POS Phy with Utopia Level 3, POS-PHY Level 3/SPI-3 & PECL}
Xilinx {FPGA Cores, and Interfaces}
SPI4 Description and SPI4 Devices
Engineering Design Key words: SPI-3, Optical Transport Network, OTN, SONET Bus, SDH, Synchronous Optical NETwork, Electrical Standard, Interface Standard, Specification, Spec, Fiber, Electrical Interface, Data Rate, IC Semiconductor manufacturers, Physical Interface, Engineering Description, electrical characteristics, Component Manufacturers, Optical Carrier, Line-Terminating Equipment, LTE, Path-Terminating Equipment, PTE
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