The S-100 bus was developed in 1975 to accommodate the Intel 8080 processor and TTL technology of the era. It operates at up to several MHz based on the master processor's clock rate. It has two 8 bit data paths, a 16 bit address bus and 8 Interrupt lines. I/O lines are Totem Pole TTL Outputs or open collector driver/receivers. Power to boards is +/- 18 volts, +/-8 volts with on-board regulators. The IEEE-696 bus, an early 1980's revision, operates at up to 10MHz with an 8 or 16 bits data bus, a 24 bit address bus, and supports multi-master and slave boards. The S-100 and IEEE-696 cards use 100-pin edge connectors with .1 inch spacing, on a 10" X 5" card set mounted in a card cage on a typically passive backplane or "Motherboard". The S-100 bus was initially developed in 1975 by MITS as a 100-pin bus for the MITS Altair 8800, among the earliest of Intel 8080-based microcomputers. Essentially it reproduces the signals from the Intel 8080 processor, and supported a front panel of lights and switches. It became "the S-100 bus" after several companies, starting with IMSAI, copied the bus to create plug-compatible boards and systems. By the late 1970's over 100 companies produced S-100 type products. During that time, several designers worked with the IEEE to develop a standard master/slave architecture with 24-bit addressing and 16-bit data path. This became the IEEE-696 standard, published in 1983. IEEE-696 products were produced well into the 1980's but were not competitive with smaller boards and highly integrated computing products. The IEEE removed this standard in the late 1990's.

A history of the S-100 bus and bus signals for early S-100 buses and the IEEE-696 bus are in this document: www.retrotechnology.com/herbs_stuff/s100bus.html
Herb Johnson, June 29 2007