Leroy Davis
Melbourne, FL
interfacebus.com@gmail.com
http://www.interfacebus.com/

OBJECTIVE:    Team Lead, System Specifications, Board Designer, FPGA Designer

EDUCATION:
B.S. Degree in Electrical Engineering Technology, May 1984: Old Dominion University, Norfolk, Virginia

EMPLOYMENT:

Harris Corporation, Melbourne Florida, May 5 1997 - Present        Electrical Engineer III
Board lead, 16 layer 10Gig OTN card, DDR2 Memory, 4 FPGAs.
Board lead 14 Layer PWB [Circuit Board design lead], with 7 FPGA's, running 66MHz clocks.
Lead Hardware Engineer, on a multi-chassis (VME), Radar Simulator.
Supervised the redesign of 2 PWBs [Printed Wiring Board] and 3 FPGAs, and the documentation.
Supervised the design of 1 Circuit design/PWB and 1 FPGA, and the documentation.
Supervised a number of Engineers and Technicians
Generated or Supervised a number of CDRs and PDRs [Critical Design Reviews]
Produced specifications defining 4 separate 21 slot VME chassis [Military Rugged].
Designed a Xilinx 4005 FPGA using VHDL and Synopsis, to control data I/O into a FIFO.
Designed a Xilinx 4013 FPGA in VHDL which controlled a number of devices on a PCB.
Redesigned an Altera CPLD, using Altera's MAXPlus2 [VHDL and Schematic design].
Developed a Printed Wiring Board using Cadence schematic capture.
Wrote a number of Hardware Description Specifications (HDS), for PWBs and FPGAs
Military mobile ground systems, Military/DOD standards and Specifications
BackPlane design: VME, cPCI / HSSI systems, Custom Back Planes

Alliant Tech Systems, Annapolis Maryland, October 2 1995 - April 25 1997        Senior Design Engineer
Designed an ‘Altera’ FPGA to enable automatic signal routing for a product test set.
Designed an ‘Altera’ FPGA using both AHDL and schematic entry, simulation using the MAXPlus2 software.
Produced a PC104 extension PWB, for testing {one-for-one pin connections}
Worked with Printed Wiring Board vendors implementing IPC-RB-276 specifications.
Investigated different modifications to lap-top PCs, for rugged-ized operation, centered around the ATA [ IDE ] spec.
System Engineering on a VME / RaceWay based Radar Simulator, UNIX operating system.
Supervised the modification and layout of a number of Printed Circuit [PC] boards.

HRB SYSTEMS, Stafford Virginia, July 9 1990 - June 4 1995        Advanced Engineer
Designed a Memory card (VME form factor) with automatic recycle capability.
Designed a Synchro to Digital converter card to control an antenna pedestal {no production}.
Designed a VME interface card with BLock Transfer (BLT) capability, using 22V10 PLDs, with ABEL.
Designed a 200MHz Time of Arrival [TOA] card, using the ECLinPS series of ECL [Emitter Coupled Logic].
Designed an asynchronous DRV11WA (uVAX) to HP FIFO interface card.
Designed a Memory card with DMA, controlled by a DRV11J and interfacing to a DRV11WA (uVAX).
Designed a 20MHz Memory / FIFO card with DMA capability to a DRV11WA (uVAX).
Designed a 20MHz A/D converter card interfacing to a custom backplane.
Wrote a number of Interface Control Documents (ICD) specifying current system configuration.
These designs were all Euro-Card 6U format in a standard 8U chassis with a custom backplane, controlled by a DEC microVAX.
Lead Hardware Engineer, operational government field site; maintain and upgrade site hardware.

National Security Agency, Ft Meade Maryland, September 23 1985 - July 6 1990        Associate Engineer
Worked in the secure communications area, designing and evaluating secure voice equipment, and detection equipment.
Designed the black section of a 10 channel STU III automatic digital conferencer, which interfaced to the public phone system.
The STU III design included a 8051 micro-controller programmed in C.
Designed a 100MHz (delay and multiple) chip rate detector, using both 10KH ECL and AS TTL devices.
Designed an IEEE-488, GPIB standard (listen only) interface with DMA capability [in-house common lab equipment interface].
Designed and wire-wrapped a 20MHz 16 to 32 bit comparator circuit to flag bus errors [in-house lab test circuit].
Designed a 20MHz D/A converter to test an in house digitizer [Low-noise].
Evaluated new equipment and signal analysis software routines [to include operational software testing].
Performed market surveys to up-date and replace existing hardware.

Pulse Communications, Herdon, Virginia May 14 1984 - September 17 1985
Worked in the digital telephone area developing voice grade transmission (2 to 4 wire) modules, interfacing to a T1 link.
Designed, prototyped, and tested various D4 channel bank cards.
Design responsibilities included accepting a concept from the marking department, setting up a design schedule, and generating test specifications.
Interacted with other departments to oversee component acquisition, schematic generation, PC board layout, and production testing.
Introduced two (redesigned) products into the market place. Two separate D4 module cards designed by another engineer.
Generated test specifications which were passed to the test department.
These tasks also included the design of digital logic [74HCxx series] to control time divisional multiplexing and
analog operational amplifiers to buffer and amplify voice signals. These CCA's measured about the same size as a PC expansion card.

Security Clearance:
TS/SCI SBI: ~ 01/10/04 active; CI Polygraph

For a printable version of the above resume, see the resume.html page
For a one page version in MS Word, see the Resume.doc page

Key Words: Electrical Engineer, Digital Hardware Engineer, Electronic Engineer, PWB Board Designer, FPGA Designer, VHDL Programmer, Resume, CCA,
Circuit Card, Printed Wiring Board, PWB, Military Standards, Military Specifications, Ground Systems, Interface Specifications, Computer Buses, FPGA Buses.

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