Dictionary of Engineering Terms
"A"
"B"
"C",
"D",
"E",
"F",
"G",
"H",
"I",
"J",
"K",
"L",
"M",
"N",
"O",
"P",
"Q",
"R",
"S",
"T",
"U",
"V",
"W",
"X",
"Y",
"Z"
Note the definitions relate to PLDs, while the alphabetic links above contain other engineering definitions.
ABEL Advanced Boolean Expression Language. A Hardware description language [HDL], a programming language used to program Programmable Logic Devices [PLDs].
Active High. Output is a logic high when the Sum-of-Products expression is true. [Non-inverted Output]
Active Low. Output is a logic low when the Sum-of-Products expression is true. [Inverted Output]
Complex Programmable Logic Device [CPLD] A high density programmable device generally based on the PAL or SPLD architecture. The routing structure leads to more predictable timing than the FPGA.
Digital Signal A digital signal is one whose key characteristic (e.g., voltage or current) fall into discrete ranges of values. The interpretation of an analog signal would correspond to a signal whose key characteristic would be a continuous signal. Most digital systems utilize two voltage levels. Systems with more than two levels include MIL-STD-1553 bus. There are three ranges defined (with several keep out zones). Newer flash memory devices utilize four levels for storage, doubling the bit density to two bits per cell.
Erasable Programmable Logic Device. [EPLD] A PLD that may be erased once programmed, and than programmed again. Depending on the PLD, the device may be erased by applying a higher voltage to a specific pin or an ultraviolet light through a window provided on the body of the PLD.
Fanout. The number of additional IC gates a PLD output can drive. Fan-Out is determined by the current the gate can source and sink. Expanded FanOut definition.
Field Programmable Logic Array. [FPLA] And/Or/Invert architecture with three level fusing. An FPLA use a programmable AND array followed by a programmable OR array. Refer to the FPLA graphic in the right side-bar.
Field Programmable Logic Sequencer. [FPLS] A Full Mealy state machine. Programmable AND and OR planes.
Field Programmable Gate Array. [FPGA] This device is similar to the gate array, defined above, with the device shipped to the user with general-purpose metallization pre-fabricated, often with variable length segments or routing tracks. The device is programmed by turning on switches which make connections between circuit nodes and the metal routing tracks. The connection may be made by a transistor switch (which are controlled by a programmable memory element) or by an antifuse. The transistor switch may be controlled by an SRAM cell or an EPROM/EEPROM/Flash cell. Timing is generally not easily predictable. Some architectures employ dedicated logic and routing resources for optimizing high-speed functions such as carry chains, wide decodes, and so on. [Programmable Logic Manufacturers]
Gate Array Transistors or gates are fabricated in a 2 dimensional array on a die to form the standard base of an application specific integrated circuit [ASIC Manufacturers]. The devices is programmed by custom metal layers interconnecting nodes in the array. Some gate arrays have other features such as SRAM blocks, phase lock loops, delay locked loops, etc.
Generic Array Logic [GAL] Another form of programmable logic device using EEPROM bits. See the GAL20V8 in the right side-bar.
I/O Bank A group of Input/Output [I/O] pins that use the same power and ground pins, which are separate power pins used by another I/O bank. The size or number of I/O within the bank differs between devices, there is no set I/O bank size. Also refer to an I/O Bank Graphic.
Macrocell A higher order cell that contains flip flops, Muxs or other higher order functions in addition to AND/OR cell functions. For reference; a 22V10 Macrocell graphic is provided.
One Time Programmable. [OTP] A semiconductor device, such as a PROM or PLD, that may be user programmable only once, but once programmed the device may not be reprogrammed. An OTP device does not require a window for UV erasing, or a separate pin or voltage for erasing. Many standard PLDs such as the 22V10 are available both as a re-programmable device or a One-Time Programmable option, depending on the part number specified [MIL-M-38510/508; C22V10].
Product Term. Logical AND operation on input variables.
Programmable Logic A logic element whose function is not restricted to a particular function. It may be programmed at different points of the life cycle. At the earliest, it is programmed by the semiconductor vendor (standard cell, gate array), by the designer prior to assembly, or by the user, in circuit. [Programmable Logic Manufacturers]
Programmable Logic Array [PLA] This device has both programmable AND and OR planes. PLA structures may also appear as part of some CPLDs. The two layers of programmable structure add a fixed delay.
The PROM, PAL, AND PLA are three related devices. They share an architecture that consists of AND and OR planes [Matrix]. Additional features such as programmable I/O blocks, storage registers, etc., may be included in these devices. Commercial, military, and space devices use a variety of programmable elements. A complete list is beyond the scope of this tutorial. Some aerospace examples are given below.
Programmable Read Only Memory. [PROM] This device has a fixed, fully decoded AND plane and a programmable OR plane. The programmable element for these devices include EPROM, EEPROM, fuses and antifuses. Fuse materials include nichrome and polysilicon elements. Antifuse structures may consist of Oxide-Nitride-Oxide or amorphous silicon material. Other elements are possible and may be used in some devices. [PROM IC Manufacturers]. [EPROM Definition]
Programmed Array Logic [PAL] This device has a programmable AND plane and a fixed OR plane. Many commercial/military devices use fuses - one device family uses EEPROM cells and logic (CoolRunner). These are often referred to as Simple Programmable Logic Devices (SPLDs).
Programmable Read Only Memory PROM Memory devices, use the standard PROM diode matrix, with the addition of input decoders and output buffers.
Simple Programmable Logic Devices [SPLDs]
Standard Cell This device differs from the gate array since each cell may be different and optimized for each standard function. There are no standard layers to the device and each layer of the chip is a unique design.
Summing Term. Logical OR operation on product terms.
