FET Derating Curves

High Temperature FET Design

2N6760 FET [TO-204AA package]
IRF330; 400V Single N-Channel Hi-Rel MOSFET in a TO-204AA package

2N6760 FET Maximum Case Temperature Vs Drain Current Derating Graph
2N6760 Max Drain Current vs Temp

Be sure to pay close attention to how the graph is labeled. The two most common means of rating a semiconductor is by case temperature or air temperature, but both are designed to limit the maximum semiconductor junction temperature.

In all situations the text or the graph will indicate the semiconductor package the graph relates to, otherwise it would be hard to make any kind of assessment. However in some cases the data sheet might also indicate a particular style of board mounting or other limitation that needs to be followed.

Derate the Drain current of the 2N6760 as specified by the maximum case temperature in the chart above. Never allow the junction temperature to exceed 150C as indicated in the graph.
Note the required decrease in Drain current as the case temperature increases. To allow for maximum component life, operate the 2N6760 well below the curve shown in the graph above. Apply force air cooling as required to obtain a higher drain current, because the graph only goes up to the maximum allowable junction temperature. Increased cooling is required to allow the 2N6760 to pass a high drain current while still keeping the junction temperature below its maximum.

2N6760 Maximum Ratings
Voltage Gate to Source = 20 volts dc
Voltage Drain to Source = 400 volts dc
Voltage Drain to Gate = 400 volts dc
2N6760 Junction Temperature = -55 to +150oC

MIL-PRF-19500/542; Semiconductor Device, Transistor, Field Effect, N-Channel, Silicon, Types 2N6756, 2N6758, 2N6760, 2N6762, implemented in a metal TO-204AA package.
Implementation note; this package formerly had the JEDEC outline of TO-3 [out-dated].
These parts are qualified to JAN, JANTX, JANTXV, JANS, JANHC, and JANKC.

Also refer to FET Derating Guidelines, or Transistor Derating Guidelines.

TO-204 Case mount. A type of package which provides a method of readily attaching one surface of the semiconductor device to a heat dissipater to achieve thermal management of the case temperature. The Drain of the 2N6760 is electrically connected to the case. Refer to the link for terminal identification. Note that the dimensions and more details on this package style are provided by the link which covers this case style. As shown in the internal circuit schematic this device also contains an internal protection diode across the Drain and Source terminals. The diode is internal to the package and is an integral part of the device.

Compensating for case temperature rise; Electronic Component Derating

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Home > Circuit Design > Logic Design > Component Derating > FET Derating > 2N6760 FET.

Internal circuit schematic for a 2N6760 Field Effect Transistor
Circuit Schematic

2N6760 TO-204 Package Drawing, Case OutLine
TO-204 Package Outline

The case is the third terminal.
The Drain is connected to the metal case.

Vendors & Manufacturers:
FET Manufacturers
Thermal Test Chambers
Thermal Imager Manufacturers
Thermal Sensor Manufacturers
Note the links to test gear.

The specification revision is omitted.
The revision level may change at any time.
The standard may be removed at any time.

PC motherboard

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Modified 6/13/15
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