The Low Pin Count [LPC] Bus, may also be called PPC.
The LPC Interface allows the legacy I/O motherboard components, typically integrated in a Super I/O chip, to migrate from the ISA/X-bus to the LPC Interface.
The LPC Interface Specification describes memory, I/O and DMA transactions, and uses the PCI 33MHz clock.

LPC was developed by Intel. The version of the specification I've seen dates to 2002.

The Low Pin Count interface specification makes a number of references to the ISA bus, so this may have been a transitional interface during the ISA / PCI trade-off phase ~ during the time an ISA expansion slot resided next to a PCI expansion slot.

The LPC interface is motherboard only and does not use a connector, or provide an expansion slot.

This may be a legacy interface as the ISA and PCI buses are replaced by the PCIe interface.

The SST 49LF040B, 4 Mbit Flash is an example of an IC using the Low Pin Count [LPC] interface.
A 32-pin PLCC SST49LF040B 4Meg [512k x 8] Flash IC, attached to a Printed Wiring Board [PWB] is shown left.
Low Pin Count Pinout
LCLK [Clock], A PCI compatible input clock.
LAD[3:0], A 4-bit Input/Output Data/Address interface Bus.
LFRAME#, An input to indicate either the start of a data transfer operation or used to abort an LPC cycle in progress.
Related I/O into the 49LF040B LPC block:
ID[3:0], These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0]=0000, all subsequent devices should use sequential count-up strapping. These pins are internally pulled-down with a resistor between 20-100K ohm.
INT#, A input pin to reset the device.
GPI[4:0], General Purpose Inputs, The state of these pins can be read through GPI_REG (General Purpose Inputs Register). Unused GPI pins must not be floated.