Low Pin Count

LPC Description

LPC defines the protocol for an electrical interface between motherboard components.
No connector or mechanical interface is defined by the LPC interface.
The LPC interface was meant to be an interim solution as the ISA bus was being phased out.
Providing a software compatible ISA bus, which really used a minimum hardware [low pin count] interface.
LPC was meant to facilitate the industry's transition toward legacy free systems [legacy free means no ISA bus].

The Low Pin Count [LPC] Bus, may also be called PPC [undefined acronym].
The LPC Interface allows the legacy I/O motherboard components, typically integrated in a Super I/O chip, to migrate from the ISA/X-bus to the LPC Interface.
The LPC Interface Specification describes memory, I/O and DMA transactions, and uses the PCI 33MHz clock.
Recall that the ISA bus only used an 8MHz clock, although the ISA interface had a wider interface bus.
LPC was developed by Intel. The version of the specification I've seen dates to 2002, with no updates.

The Low Pin Count interface specification makes a number of references to the ISA bus, so this may have been a transitional interface during the ISA / PCI trade-off phase ~ during the time an ISA expansion slot resided next to a PCI expansion slot.

The LPC interface is motherboard only and does not use a connector, or provide an expansion slot.

This may be a legacy interface as the ISA and PCI buses are replaced by the PCIe interface.

The document is Low Pin Count (LPC) Interface Specification, Revision 1.1, Aug 2002 [initial release in 1998]

The SST 49LF040B, 4 Mbit Flash is an example of an IC using the Low Pin Count [LPC] interface.
A 32-pin PLCC SST49LF040B 4Meg [512k x 8] Flash IC, attached to a Printed Wiring Board [PWB] is shown left.

49LF040 Flash PLCC mounted on a PCB
49LF040B Flash

Low Pin Count Pinout
LCLK [Clock], A PCI compatible input clock.
LAD[3:0], A 4-bit Input/Output Data/Address interface Bus.
LFRAME#, An input to indicate either the start of a data transfer operation or used to abort an LPC cycle in progress.
Related I/O into the 49LF040B LPC block:
ID[3:0], These four pins are part of the mechanism that allows multiple parts to be attached to the same bus. The strapping of these pins is used to identify the component. The boot device must have ID[3:0]=0000, all subsequent devices should use sequential count-up strapping. These pins are internally pulled-down with a resistor between 20-100K ohm.
LRESET#, [INT#], A input pin to reset the device.
GPI[4:0], General Purpose Inputs, The state of these pins can be read through GPI_REG (General Purpose Inputs Register). Unused GPI pins must not be floated.

In LPC mode, communication between the Host and the 49LF040B occurs via the 4-bit I/O communication signals, LAD[3:0] and LFRAME#.
The 49LF040B detects the start of an LPC cycle by reading the START field contents; a 0000b indicates the beginning of an LPC memory cycle.

There are several other optional signals [not used with the 49LF040] which include;
LDRQ#. Encoded DMA/Bus Master Request; indicating a peripheral needs a DMA.
SERIRQ. Providing interrupt support to peripherals.
CLKRUN#. Same as PCI CLKRUN#, used to stop the PCI bus.
LPME#. LPC Power Management Event, similar to PCI PME# to wake up from a low-power state.

It does appear that the last revision of the Low Pin Count interface specification was released by Intel in 2002.
So the interface would be considered a legacy interface standard, out-dated, if not obsolete.
No longer required as the ISA buses are long gone, and the PCI interfaces are also disappearing.
The LPC specification makes reference to an X-bus which seems to be an undefined reference to a ISA-to-PCI bridge.
Although, because the document does not define what the X-bus is, it's a bit hard to tell what the X-bus relates to.

In any even the ISA interface is obsolete and has been out-dated fro more than 10 years.
The PCI bus is also out-dated, having been replaced by the PCIe bus more than half a dozen years ago.
In other words if the ISA bus is obsolete and no longer used, there is no need to bridge the interface between ISA and PCI.

However a number of other interfaces call out the Low Pin Count signals.
Their attempt to produce a legacy free standard which would not support legacy [ISA] functionality.
COM Express is an example of a standard using the LPC interface, instead of defining PS/2 keyboard/mouse, serial ports, and parallel ports.
COM Express is an embedded computer board standard, released around 2004.

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Modified 1/22/12
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