Digital Logic Noise and EMI Issues

Digital logic design pitfalls are listed below. The best way to avoid these logic pitfalls is to start a Timing budget, and Noise budget which would allow these issues to be designed out, or force these issues to be designed out. In most cases, not designing out these pitfalls will result in Intermittent failures of ICs during operation. Random data errors will result, or unexpected circuit operation can be expected if any of the conditions below are allowed to exist. The worst issue involving any of these hazards is that they may produce a data error at any random time. Designers may expect a failure once a day, or once a week ~ from the same case on the same board.

Dynamic Hazards: Random glitches or signal transitions result of poor combinational logic design. See Timing Hazards below..

EMI: [Electro Magnetic Interference] or RF [Radio Frequency] problems are both noise issues. Either of these problems are caused by any number of design problems [some listed below]. Current loops are a major problem.

Ground Bounce: defines a condition when a device's output {really a number of outputs} switches from High to Low and causes a voltage change on other pins. The problem is cause by the large current flow through the ground pin which develops a voltage drop over the lead inductance. This voltage drop on the ground line creates two main problems; first it rises the chip off ground [0 volts] potential which increases the devices input threshold level, and increases the voltage level on an output pin which is not switching. Because a quiet output is effected by the other switching outputs, this is also called Simultaneous Switching Noise. It's really a question of loss of noise margin which is listed below. The faster the slew rate of the logic family, the worse the problem becomes. With glue Logic, the ground pins may have been moved around to reduce the inductance. Using a surface mount device instead of a Through Hole will reduce the lead inductance. For FPGA's with hundreds of possible output pins the situation may change, and it's more up to the designer. Start a noise budget to determine if the ground bounce [rise in ground potential] effects the design. The voltage developed over ground lead is proportional to the rate of change in current, so the faster the logic family the worse the problem becomes: V = L * [di/dt]. The more outputs switch at the same time, the larger the current value, and the greater voltage bounce. Also occur when the outputs switch from a 0 to a 1 but to a much smaller degree. Series termination of the line is one method of reducing ground bounce. Series termination resistors slow the rate of change of the output, and so reduce the instantaneous current on the ground line. Also Resistor Pull-Ups on the line cause the ground bounce voltage to increase. The pull-up resistor allows the load capacitor to charge to it's flow value, so as the line switches maximum current is delivered back to the driver. Eliminate pull-up resistors on devices with an issue, use pull-down resistors or series resistors if possible. Reducing the loading on the driver also reduces ground bounce.

Ground and Power Planes: Design Links only ~ no information yet. For [almost] any glue logic family a complete ground plane is required. If the power plane is placed next to the ground plane the design has a benefit: the power plane is coupled to the ground plane. A common mistake is to assume that because the IC clock rate is low, no ground plane [or power plane] is require. However, the important frequency involved the the switching rate, or signal rise time. In many cases the rise time is on the order of 1 to 2nS, regardless of the clock rate. A design that uses a signal period [CLK] of 50MHz with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz. Or a clock of 100KHz, with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz.

Jitter: Digital Logic Jitter Definitions

metastability: Logic metastability is caused by violating the Set-up and Hold times of a Flip Flop. Normally the violation is caused by an asynchronous data signal input to a clocked Flip Flop. The resulting Flip FLop output may stay undefined for some time, or oscillate. MTBF equations are provided.
The resulting oscillations are noise.

Noise Margin: defines the difference in voltage between what the driver will output as a valid logic level, and what the receiver will accept as a valid logic level. There are a number of factors which could reduce the noise margin in a design. The greater the noise margin the better the device will ignore noise on the signal lines.}

Resistor Pull-Up values: Determine how to calculate resistor pull-up values for inputs or outputs to eliminate slow signal rise times [Open Collector outputs] or invalid logic states [Tri-State outputs].

Reflections: Signal reflections on the trace are caused by a number of conditions. Avoid discontinuities on PWB traces; changes in the impedance of the trace will cause reflections. Termination of traces will reduce or eliminate reflections from the 'far-end' IC; see Trace Termination Schemes for the primary reason. Additions causes include: Sharp bends; the cross-sectional area of the trace increases at the bend lowering Zo. Vias; Vertical run between board layers is an uncontrolled impedance. Layer changes; Moving from an outside layer {stripline} to an inside layer {microstrip}. Avoid stubs on the signal lines, stubs are really traces that require a termination resistor.

Simultaneous Switching Noise: A change in voltage level on a quiet [un-changing] output of a device caused by the other outputs switching on the same device. See Ground Bounce, and then Noise Margin.

Static Hazards: See Timing Hazards listed below. Logic hazards generate glitches in combinational logic, which are by definition; noise

Timing Hazards: may be either Static Hazards and Dynamic Hazards and are caused by timing variations which have not been accounted for in the design. Timing Hazards generate unwanted signal transitions.

Trace Termination Schemes: help prevent signal reflections from occurring between a driver and receiver. Resistor Trace Termination methods eliminate unwanted reflections in a cable or PWB trace. A common mistake is to assume that because the IC clock rate is low, no termination is require. However, the important frequency involved the the switching rate, or signal rise time [Tr]. In many cases Tr is on the order of 1 to 2nS, regardless of the clock rate. A design that uses a clock [CLK] of 50MHz with a Tr of 1.1nS has an Effective Operating Frequency of 318MHz. Or a CLK of 100KHz, with a 1.1nS Tr has an Effective Operating Frequency of 318MHz. It's the same regardless of operating frequency.

Voltage Droop, Output: defines the loss in output voltage from a device as it tries to drive a [capacitive] load. The value of the Decoupling Capacitor that should be used or an IC depends on your load the IC has to drive. If device A has to drive two separate inputs at 3.3 volts then the load depends on the load of both inputs, taking into consideration the rise time of the signal. The input capacitance for a given device is parameter Ci in the device data sheet. If the receiver [B] has a load of 12pF [Ci] and the output driver [A] has a rise time of 1nS then the current required is: I = dV / dt or I = 12pF*(3.3v)/1nS. The current required = 39.6mA. If we keep the voltage droop to 3.0 volts, or a reduction of 300mV. The capacitor then equals: C = I * dt / dV. C = 39.6mA * 1nS/300mV = 22pF

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Modified 1/25/12
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