Logic Family Noise Margin

Digital Logic Slew Rate and Switching Diagram

The graphic above indicates the the difference between V_OH and V_OL, in general.
The graph also provides an equation for determining IC slew rate and gives an indication of the logic speed [using the voltages below].
The table below provides data for Noise Margin for each of the logic families listed.

Noise Margin Calculation
Logic Noise Margin is the difference between what the driver IC outputs as a valid logic voltage and what the receiver IC expects to see as a valid logic voltage. There are two different types of noise margin, one for a logic high value [1] and one for a logic low value [0]. For a valid logic high, the worst case noise margin for the circuit is the minimum high level voltage which may be output from the driver; minus, the minimum high level voltage which may be seen at the receiver IC. For a valid logic low, the worst case noise margin for the circuit is the maximum low level voltage which may be output from the driver; minus, the maximum low level voltage which may be seen at the receiver IC. The equations for noise margins are provided below, use the minimum of maximum numbers as described above.

Noise Margin Output high = V_OH [driving device] - V_IH [receiving device]
Noise Margin Output low = V_IL [receiving device] - V_OL [driving device]
The higher the numbers the better, with negative numbers indicating in-operability [no Noise Margin].
Use Minimum numbers for output High, and maximum numbers for Output Low to calculate Noise Margin.

**Noise Margin**
--	VOH	VIH	Margin	VIL	VOL	Margin
TTL [5volt]	2.4v	2.0v	400mV	0.8v	0.5v	300mV
FCT [5volt]	2.5v	2.0v	500mV	0.8v	0.5v	300mV
BTL [5 volt]	2.1v	1.62v	480mV	1.47v	1.1v	370mV
GTL [5 volt]	1.5v	1.05v	450mV	0.95v	0.55v	400mV
CMOS [5 volt]	4.9v	3.85v	1050mV	1.35v	0.1	1340mV
LVTTL [3volt]	2.4v	2.0v	400mV	0.8v	0.4v	400mV
LVCMOS [3 volt]	2.8v	2.0v	800mV	0.8v	0.2v	600mV
CMOS [2.5v]	2.0v	1.7v	300mV	0.7v	0.4v	300mV
CMOS [1.8v]	1.35v	1.1v	250mV	0.66v	0.45v	210mV

The Noise Margins listed in the table are IC to IC within the same logic family. If you mix logic families the Noise Margin will need to be re-calculated using the noise margin equation listed above. The table also shows that the noise margin does not really get smaller as the voltage is reduced or as the logic family changes. Also note that the noise margin in CMOS is higher than the noise margin in TTL for 5 volt logic levels.

So ..... Why do I care about noise margin? How does noise margin effect my design? What changes effect noise margin?

Digital logic devices switch between two [and only two] states, high [1] and low [0]. The higher the noise margin, the greater the difference between what is considered a valid high or a valid low ~ with out going into an undefined region [a voltage not considered high or low]. So a valid high [for a particular digital logic family] may be between 2.4 volts and 2.0 volts. For one IC to communicate with another IC, a logic high may reside between 2.4 volts and 2.0 volts. Producing a maximum valid voltage or noise margin of 400mV. If you have ground bounce issues, power voltage droop issues, trace reflection issues, trace coupling issues or another problem which will reduce the input receiver IC voltage as a posed to what the driver IC outputs will reduce the noise margin ~ which is why a higher noise margin is better. If a design problem results in a negative noise margin then the receiver will see neither a valid logic high or low, so what does the receiver see? I don't know, what ever it wants ~ which means it's output will switch to what ever it has to [an invalid level].

Terms -

V_CC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at.

V_IH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high.

V_IL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low.

V_OL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level.

V_OH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level.

V_T: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.

A graph for Standard voltage devices resides on the Logic Voltage Threshold page.
An additional chart of Low Voltage [LV] logic threshold levels is provided on the Low Voltage Threshold Interface Level page.
Another chart of Interface bus threshold levels is provided on the Interface Threshold Voltage Level page.

Description of TTL, ECL and CMOS Glue Logic Families

Device Families: TTL (74xx) True TTL 74L Low power 74S Schottky 74H High speed 74LS Low power - Schottky 74AS Advanced - Schottky 74ALS Advanced - Low power - Schottky 74F(AST) Fast - (Advanced - Schottky) 74C CMOS...................check Vcc levels 74HC (U) High speed - CMOS (Unbuffered output) 74HCT High speed - CMOS - TTL inputs 74AHC Advanced - High speed - CMOS 74AHCT Advanced - High speed - CMOS - TTL inputs 74FCT (-A) Fast - CMOS - TTL inputs (speed variations) 74FCT (-T, -AT) Fast - CMOS - TTL inputs (speed variations) 74AC Advanced - CMOS 74ACT Advanced - CMOS - TTL inputs 74FACT AC, ACT (Q) series 74ACQ Advanced - CMOS - Quiet outputs 74ACTQ Advanced - CMOS - TTL inputs - Quiet outputs Bus Driver Families 74ABT Advanced - BiCMOS - Technology 74ABTE ABT - Enhanced Transceiver Logic 74ABTH Advanced - BiCMOS - Technology - bus Hold 74BCT BiCMOS - TTL inputs 74BTL Backplane - Transceiver - Logic 74GTL Gunning - Transceiver - Logic 74GTLP GTL (Motorola) Low Voltage Families 74ALB Advanced - Low Voltage - BiCMOS 74LV (U) Low - Voltage (Unbuffered output) 74LVC (R) (U) LV - CMOS (damping Resistor)(Unbuffered output) 74LVCH Low - Voltage - CMOS - bus Hold 74ALVC Advanced - Low - Voltage - CMOS 74LVT (R) (U) LV - TTL (damping Resistor(Unbuffered output) 74LVTZ Low - Voltage - TTL - High Impedance power-up 74ALVC (R) ALV - CMOS (bus Hold) (damping Resistor) 74ALVCH Advanced - Low - Voltage - CMOS - bus Hold 74LCX LV - CMOS (operates with 3v & 5v supplies) 74VCX LV - CMOS (operates with 1.8v & 3.6v supplies 4000 True CMOS (non-TTL levels) ECL Device Families: MEC I 8nS* MEC II 2nS* MEC III (16XX) 1nS* .......* = Rise & Fall Times 101xx 100 series 10K ECL, 3.5nS* 102xx 200 series 10K ECL, 2.5nS* 108xx 800 series 10K ECL, voltage compensated, 3.5nS* 10Hxxx 10K - High speed, voltage compensated, 1.8nS* 10Exxx 10K - ECLinPS, voltage compensated, 800pS* 100xxx 100K, temperature compensated 100Hxxx 100K - High speed, temperature compensated 100Exxx 100K - ECLinPS, temp, voltage comp., 800pS*

**Related pages on this site:**
Standard Logic Voltage Thresholds	Interface Logic Thresholds	Glue Logic Speed x Power Chart	How to Termination Traces	Ground/Power Planes

Back to the Logic Design Page

Definition for logic family terms:
TTL: Transistor Transistor Logic
ECL: Emitter Coupled Logic
CMOS: Complementary metal-Oxide Semiconductor
BICMOS: Bipolar Complementary metal Oxide Semiconductor
IC: Integrated Circuit

ECL Noise Margin;
Noise margin for ECL components is not covered here, but there are some general comments.
The noise margin changes depending on what ECL family is driving what ECL family [mixing types lowers the margin]
The noise margin for 10K ECL driving 100K is much better than 100K ECL driving 10K ECL.
In addition to changes due to interfacing, noise margins will also change based on operating temperature.
In fact the noise margin might increase or decrease over 100 mV over the operating temperature range.


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