Digital Logic Pitfalls

Digital logic design pitfalls are listed below in alphabetic order. The best way to avoid these logic pitfalls is to start a Timing budget, and Noise budget which would allow these issues to be designed out, or force these issues to be designed out. In most cases, not designing out these pitfalls will result in the Intermittent failures of ICs during operation. Random data errors may result, or unexpected circuit operation can be expected if any of the conditions listed below are allowed to exist. The worst issue involving any of these hazards is that they may produce an unexpected data error at any random time. Designers may expect a failure once a day, or once a week ~ from the same cause on the same board.

IC Bus-Hold Input Pins: Do not terminate IC pins that have Bus-Hold input circuitry.

Component Over Heating: De-rating component specifications based on temperature rise. Choosing component specifications which exceed the operating environment produces decreased failure rates. Device operating temperature, voltage and current may all be de-rated to increase the operational life of the component. Derating a components characteristics amounts to insuring that the device's parameters exceed the circuit parameters the device encounters. The page link provides de-rating rules to apply for different types of components.

Dynamic Hazards: Random glitches or signal transitions as a result of poor combinational logic design. See Timing Hazards below..

EMI: [Electro Magnetic Interference] or RF [Radio Frequency] problems are both noise issues. Either of these problems are caused by any number of design problems [some listed below]. Current loops are a major problem.

FanOut : Integrated Circuit [IC] Fan-Out is the ability of one device to drive some number of other devices.

Ground Bounce: defines a condition when a device's output {really a number of outputs} switches from High to Low and causes a voltage change on other pins.

Ground Loops: Additional information and design rules

Ground and Power Planes: Design Links only ~ no information yet. For [almost] any glue logic family a complete ground plane is required. If the power plane is placed next to the ground plane the design has a benefit: the power plane is coupled to the ground plane. A common mistake is to assume that because the IC clock rate is low, no ground plane [or power plane] is require. However, the important frequency involved is the switching rate, or signal rise time. In many cases the rise time is on the order of 1 to 2nS, regardless of the clock rate. A design that uses a signal period [CLK] of 50MHz with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz. Or a clock of 100KHz, with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz.

Glue Logic Timing: The basics of Logic Timing and Propagation delay, still in the works..

metastability: Logic metastability is caused by violating the Set-up and Hold times of a Flip Flop. Normally the violation is caused by an asynchronous data signal input to a clocked Flip Flop. The resulting Flip FLop output may stay undefined for some time, or oscillate. Mean-Time-Between-Failure [MTBF] equations are provided.

Noise: is caused by any of the other issues listed on this page, including Signal and Phase Jitter.

Noise Margin: defines the difference in voltage between what the driver will output as a valid logic level, and what the receiver will accept as a valid logic level. There are a number of factors which could reduce the noise margin in a design.

Oscillations; Inadequate power supply bypassing. Driving a large capacitive load.
Proper supply bypassing also means using low inductance capacitors mounted near the device with short leads.
Ground loops or other grounding issues.

Oscillators or Timing circuits not working: Changes in timing circuits due to aging.

Propagation Delay: IC Propagation Delay definition, and how to avoid a logic issue

Resistor Pull-Up values: Determine how to calculate resistor pull-up values for inputs or outputs to eliminate slow signal rise times [Open Collector outputs] or invalid logic states [Tri-State outputs].

Race condition: defines a condition when a device's output depends on two [or more] nearly simultaneous events to occur at the input(s) of a device and cause the device's output to switch.

Reflections: Signal reflections on the trace are caused by a number of conditions.

Simultaneous Switching Noise: A change in voltage level on a quiet [un-changing] output of a device caused by the other outputs switching on the same device. See Ground Bounce, and then Noise Margin.

Static Hazards: See Timing Hazards listed below.

Timing Hazards: may be either Static Hazards and Dynamic Hazards and are caused by timing variations which have not been accounted for in the design.

Trace Termination Schemes: help prevent signal reflections from occurring between a driver and receiver. Resistor Trace Termination methods eliminate unwanted reflections in a cable or PWB trace. A common mistake is to assume that because the IC clock rate is low, no termination is require. However, the important frequency involved the the switching rate, or signal rise time [Tr]. In many cases Tr is on the order of 1 to 2nS, regardless of the clock rate. A design that uses a clock [CLK] of 50MHz with a Tr of 1.1nS has an Effective Operating Frequency of 318MHz. Or a CLK of 100KHz, with a 1.1nS Tr has an Effective Operating Frequency of 318MHz. It's the same regardless of operating frequency.

Timing circuits or Oscillators not working: Capacitors exhibit 'aging' or a change in capacitance value based on age. Capacitor 'Aging' is the natural process wherein X7R, X5R, Z5U, & Y5V dielectric capacitors exhibit a change in capacitance after their temperature is raised above the Curie point for their particular formulation, during soldering, or during some life time or temperature cycling tests. When the capacitor is heated above the Curie point, a change in the crystal structure occurs, and the capacitance increases. This increase in capacitance is called "deaging." As the temperature is later reduced below the Curie point, the capacitance gradually returns to its previous values. The decline in capacitance is called "aging" and occurs at a rate that decreases linearly with the log of time. C0G dielectric capacitors have a different formulation which does not display any aging characteristic. Thus, C0G dielectric capacitors have a value that remain constant with time. Circuits working one day, that rely on a capacitance value may not work the next day. Tantalum capacitors are stable over time and do not suffer from aging effects.

Voltage Droop, Output: defines the loss in output voltage from a device as it tries to drive a capacitive load.

Voltage Translation between Logic Families: is required because not all logic families have the same transition point or may switch at different levels. TTL, CMOS, and ECL have different input and output voltage levels. Other options may be available in addition to the circuits listed on that page. IC's which operate with 3.3v may only require a current limiting resistors to receive a 5 volt level. The 3.3 volt IC has protection diodes to Vcc and ground. The current limiting resistor saves the protection diode from burning up. So, in some cases a [series] resistor equal to the input voltage [Vin] - the diode drop [V diode] divided by the maximum current of the diode [Imax] will do.

Test Patterns
There are a numbers of ways to check for design or build issues with a data bus by sending different sequences of test patterns.

A few additional notes for proto-type work [assuming no simulation]:
Tack a 10pf capacitor on the load(s) to simulate worst case load conditions. Testing more then one Proto board helps as well.
Increase the clock frequency a few cycles to simulate worst case timing situations.
Reduce and / or increase the power supply voltage to simulate Vcc variations.
Reduce or divert the fan [air flow] to simulate temperature changes. Using a temperature chamber works better.
Output 0xFE in all cases to test for noise issues. If an FPGA is involved output 0xFE per bank.
Provide a massive number of test headers to sample bus and data signals, which also add load capacitance.
Always us worst case design data, Timing, Propagation delay, Trace impedance and so on

For critical signals, know if they reside on the top layer or on an inner layer ~ which make a difference, in speed and impedance.
If the prototype board layout changes before production watch for Trace layer changes on the board, the amount of via increases on a trace, increases in trace length, board material, and Fan-out changes.

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Modified 1/11/12
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