Integrated Circuit Ground Bounce
Ground Bounce: defines a condition when a device's output {really a number of outputs} switches from High to Low and causes a voltage change on other pins. The problem is cause by the large current flow through the ground pin which develops a voltage drop over the lead inductance. This voltage drop on the ground line creates two main problems; first it rises the chip off ground [0 volts] potential which increases the devices input threshold level, and increases the voltage level on an output pin which is not switching. Because a quiet output is effected by the other switching outputs, this is also called Simultaneous Switching Noise. It's really a question of loss of noise margin which is listed below. The faster the slew rate of the logic family, the worse the problem becomes.
Simultaneous Switching Bounce
With Glue Logic,
the ground pins may have been moved around to reduce the inductance.
Using a surface mount device instead of a Through Hole will reduce the
lead inductance. For FPGA's with hundreds of possible output pins the
situation may change, and it's more up to the designer. Start a noise
budget to determine if the ground bounce [rise in ground potential]
effects the design. The voltage developed over the ground lead is
proportional to the rate of change in current, so the faster the logic
family the worse the problem becomes: V = L *
[di/dt]. The more outputs switching at the same
time, the larger the current value, and greater voltage bounce. Also
occur when the outputs switch from a 0 to a 1 but to a much smaller
degree.
Series termination of the line is one method of reducing ground
bounce. Series termination resistors slow the rate of change of the
output, and so reduce the instantaneous current on the ground line. Also
Resistor
Pull-Ups on the line cause the ground bounce voltage to increase.
The pull-up resistor allows the load capacitor to charge to it's full
value, so as the line switches maximum current is delivered back to the
driver. Eliminate pull-up resistors on devices with an issue, use
pull-down resistors or series resistors if possible. Reducing the loading
on the driver also reduces ground bounce. Ground Bounce may also be
called Ground Lift.
Another out come of Simultaneous Switching [Noise] is the potential increase in propagation delay of the outputs, which could also be considered noise
Simultaneous Switching vs Propagation Delay
The chart shows the increase in Propagation Delay for a number of 48-pin packages; including, SSOP, TSSOP, and TVSOP. The longest trend line is for a 96-pin LFBGA. Note that the X-axis is number of outputs switching and the Y-axis is Propagation Delay in nS.
Additional Digital Logic Pitfalls.
VOH; Voltage Output High Voltage. The normal high level output from a gate.
VOL; Voltage Output Low Voltage. The normal low level output from a gate.
VOLP; Peak Low-level Output Voltage. The most positive [least negative] transient value of a low-level output voltage at an output that is not switching while other outputs in the same package are switching.
VOHV; Valley High-level Output Voltage. The least positive [most negative] transient value of a high-level output voltage at an output that is not switching while other outputs in the same package are switching.
