# How to Handle Tri-State Output Pins Output enable lines are control lines [labeled C in this diagram] that allow the Totem Pole Outputs to function as normal, or shut them both off depending on the state on the control line. Normally the two transistors that make up the output circuit of a transistor will function in opposition, one is conducting while the other is not. Normally an ICs output is either high or low, depending on which of the output transistors is on and conducting. When the IC is placed in the 3rd state, neither transistor is conducting and is said to be in the off-state. While in the off-state the IC will neither sink current [low state] or source current [on state], the outputs just represent a high impedance condition [Tri-state].

Tri-State Output pins should be tied to a valid logic level so the output remains fixed at a valid voltage level when the device enters TriState. Additional names for Tri-State include; High-Impedance State, or Off-State. Devices with Three-State outputs may be connected in parallel. Because only one Three-State output should be active at any given time the calculation for the pull-up resistor is the same as a normal pull-up.

VIH [max] Vcc [min] - {VResistor [min] x IIH [max]}

Another equation is used for the case when all the Tri-State devices are off, leaving the receiving gate floating. The following equation is used to calculate a pull-up resistor value so that the receiving gate is pulled high before the input rises [floats] into the transition region of the gate. To large a resistor value will slow the rise time of the gate voltage causing the voltage to linger in the transition region leading to output oscillation. The value is chosen to pull the line high before the gate floats to 0.8v.
The not to exceed float time is calculated from the leakage current on the line [IOZ] and the load capacitance [C].

Voltage/Time = IOZ / C = 20uA / 20pF = 1v/uS [these are example numbers used for the calculation]
So with in 0.8uS [800nS] the input will float to 0.8v

The formula for the required pull-up resistor value is: Vt = VCC - [e-t/RCT(VCC - Vi]      Vt = 2v, minimum voltage at time t      Vi = 0.5v, initial voltage      VCC = Supply voltage      CT = Total Capacitance, R = Pullup resistor      t = maximum input rise time.

The Resistor calculation: R = (t / 0.4 x CT). The capacitance is the trace and the addition of all the devices on the line.

You can see that the equation works for regardless of the TTL or CMOS Glue Logic Family used;
However the actual value calculated my change depending on the logic family because the leakage current will vary.
Intermittent operation or Random failure could occur if the value of the resistor is not calculated correctly. Tri-State Output Standard Tri-Stateable Output control[1G not] Bi-directional Transceiver with direction control [1DIR] Directional I/O [1AO / 1BO] Tri-state pins are usually on ICs that have to communicate over the same lines as other ICs, like bus drivers. In this example Bus B my receive data from an external source, or Bus A may driver the line out. So the line is bi-directional depending on the logic level of the control lines.

IC I/O Terms -
VCC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at. The supply Voltage.
VIH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high.
VIL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low.
VOL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level.
VOH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level.
VT: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.

IC 3-State Terms -
tZH: Output enable time (of a three-state output) to high level. The time between the specified reference points on the input and output voltage waveforms with the three-state output changing from a high-impedance (off) state to the defined high level.

tZL: Output enable time (of a three-state output) to low level. The time between the specified reference points on the input and output voltage waveforms with the three-state output changing from a high-impedance (off) state to the defined low level.

tHZ: Output disable time (of a three-state output) from high level. The time between the specified reference points on the input and output voltage waveforms with the three-state output changing from the defined high level impedance (off) state.

tLZ: Output disable time (of a three-state output) from low level. The time between the specified reference points on the input and output voltage waveforms with the three state output changing from the defined low level to a high impedance (off) state.

 . Standard Logic Voltage Thresholds . . Bus Logic Thresholds . . Logic Speed x Power Chart. . Trace Termination . . Ground/Power Planes.

Back to the Logic Design Page.

Modified 1/23/12
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