Logic Family Propagation delay

This page provides a short discussion of IC Propagation delay and how it varies as the environment or individual designs vary. Any numbers provided to indicate changes in Propagation delay are general and only used to show a relationship. Real Propagation delay numbers, or changes in Propagation delay will depend on the logic family or device used. There are dozens of different logic families, all with different propagation delays, input load values, and other characteristics. The point here is to show that if a circuit design requires the correct characteristic to operate correctly, then these additional considerations need to be accounted for. In general the propagation delay of an IC will differ from what is shown in the data sheet because of one or more of the changes in operational characteristics discussed below. However the data sheet for a device may account for some of these changes [operational temperature, V_cc variation], but usually not for increases in load capacitance.

Propagation delay increases with operating temperature. Some IC families change approximately 2nS over the entire temperature range of -50^oC to +100^oC. Some data sheets may only provide a min/max propagation delay at 25^oC.

Propagation delay may also be affected by the number of outputs switching simultaneously. The 74FCTxx family adds an additional 250pS to the Propagation delay for each output in a package switching [above the first one]. The data sheet may be providing min/max Propagation delay for one output switching or all possible outputs switching at once. If the device has 8 or 16 outputs the Propagation delay could change by a large percentage.

Power supply, V_cc variations may also effect the Propagation delay of a device. A change of 0.5nS may be expected as Vcc varies between it's minimum and maximum values. I believe it's normally inferred that this is accounted for over the normal allowable V_cc provided in the data sheet. Again, if the circuit design is operating at a speed at which Propagation delay needs to be accounted for ~ then these variations need to be accounted for.

The largest change in Propagation delay will be due to change in output Load, C_L. Normally a typical value of C_L is provided in the data sheet, the value for Propagation delay is based on this load. As the load is increased the Propagation delay increases. Some families which provide a Propagation delay number at 50pF [C_L] show an increase of 1nS per increase in load [or for each additional 50pF load]. Or, a device may have a 5nS Propagation delay with a 50pF load, 6nS Propagation delay with a 100pF load, a 7nS Propagation delay with a 150pF load and so on. So the point here is the data sheet provides a valid Propagation delay for driving one load [1 device], if the output is driving more then one load then the Propagation delay is vary different [larger]. Additional increases in load capacitance may include trace capacitance or connector capacitance or what ever happens to be on that net..

One other factor which may increase Propagation delay could be induced by adding a series termination resistor to reduce reflections on the line. Line terminations are discussed on the Trace Termination page.

So if your asking why do I care about IC propagation delay or does IC output propagation delay effect may design, or how do changes in propagation delay effect my design then you may need to account for the variations already discussed.
Intermittent operation, or failures may be seen if the variation discussed above have not been accounted for. In the lab, the power supply was always re-adjusted [for each test] to provide the correct V_cc regardless of load, while the fielded board [PWB] does not. In the lab the temperature is always 25^oC, the fielded board resides in a Humvee out in the desert. My test code pushed 2 data bits out this IC, but the real data switches all 8 bits. There were two boards [PWBs] in the test chassis while 4 boards reside in the operational chassis. If the minimum and maximum values for propagation delay is not accounted for then one board may work [having one delay] while another board with the same design may not work, because the propagation delay changed with the different chip used. Propagation delay will change from IC to IC between the listed minimum and maximum values listed on the data sheet.

The issue is a problem may not show as a failure for all fielded boards, or for boards fielded to a particular region, or it will just show as a random error with no correlation. So the rule is; follow the design rules for the particular logic family used or after the fact [once the design is done] determine what is causing the random errors [which is much harder]. Account for the propagation delay changing between the minimum and maximum values provided in the data sheet, then account for another other issue which may tend to increase the propagation delay. Don't rely on a typical value with out accounting for the variation between minimum and maximum values. Intermittent circuit operation may be seen when switching times are not accounted for.

Terms -
V_CC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at.
V_IH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high.
V_IL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low.
V_OL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level.
V_OH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level.
V_T: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.

Description of TTL, ECL and CMOS Glue Logic Families

Device Families: TTL (74xx) True TTL 74L Low power 74S Schottky 74H High speed 74LS Low power - Schottky 74AS Advanced - Schottky 74ALS Advanced - Low power - Schottky 74F(AST) Fast - (Advanced - Schottky) 74C CMOS...................check Vcc levels 74HC (U) High speed - CMOS (Unbuffered output) 74HCT High speed - CMOS - TTL inputs 74AHC Advanced - High speed - CMOS 74AHCT Advanced - High speed - CMOS - TTL inputs 74FCT (-A) Fast - CMOS - TTL inputs (speed variations) 74FCT (-T, -AT) Fast - CMOS - TTL inputs (speed variations) 74AC Advanced - CMOS 74ACT Advanced - CMOS - TTL inputs 74FACT AC, ACT (Q) series 74ACQ Advanced - CMOS - Quiet outputs 74ACTQ Advanced - CMOS - TTL inputs - Quiet outputs Bus Driver Families 74ABT Advanced - BiCMOS - Technology 74ABTE ABT - Enhanced Transceiver Logic 74ABTH Advanced - BiCMOS - Technology - bus Hold 74BCT BiCMOS - TTL inputs 74BTL Backplane - Transceiver - Logic 74GTL Gunning - Transceiver - Logic 74GTLP GTL (Motorola) Low Voltage Families 74ALB Advanced - Low Voltage - BiCMOS 74LV (U) Low - Voltage (Unbuffered output) 74LVC (R) (U) LV - CMOS (damping Resistor)(Unbuffered output) 74LVCH Low - Voltage - CMOS - bus Hold 74ALVC Advanced - Low - Voltage - CMOS 74LVT (R) (U) LV - TTL (damping Resistor(Unbuffered output) 74LVTZ Low - Voltage - TTL - High Impedance power-up 74ALVC (R) ALV - CMOS (bus Hold) (damping Resistor) 74ALVCH Advanced - Low - Voltage - CMOS - bus Hold 74LCX LV - CMOS (operates with 3v & 5v supplies) 74VCX LV - CMOS (operates with 1.8v & 3.6v supplies 4000 True CMOS (non-TTL levels) ECL Device Families: MEC I 8nS* MEC II 2nS* MEC III (16XX) 1nS* .......* = Rise & Fall Times 101xx 100 series 10K ECL, 3.5nS* 102xx 200 series 10K ECL, 2.5nS* 108xx 800 series 10K ECL, voltage compensated, 3.5nS* 10Hxxx 10K - High speed, voltage compensated, 1.8nS* 10Exxx 10K - ECLinPS, voltage compensated, 800pS* 100xxx 100K, temperature compensated 100Hxxx 100K - High speed, temperature compensated 100Exxx 100K - ECLinPS, temp, voltage comp., 800pS*

**Related pages on this site:**
Standard Logic Voltage Thresholds	Interface Bus Logic Thresholds	Glue Logic Logic Speed x Power Chart	How to Termination Traces	Ground/Power Planes

Back to the Logic Design Page, Also refer to the Delay Logic Manufacturers page

Electronic Design Key words: Propagation delay, Slew Rate, Propagation, Rise Time, Fall Time, Floating input, Glue Logic Families, Intermittent issues, Random Failures, CMOS, TTL, ECL, Speed, IC, Integrated Circuits, Propagation delay, Logic Types, logic switching levels, Output voltage, Low-Voltage, Threshold Voltage, 74xx, 74AC00, 74HC, 74AHC00, Digital Devices, Description, Definition for Logic family, Logic Terms, TTL: Transistor Transistor Logic, ECL: Emitter Coupled Logic, CMOS: Complementary Metal-Oxide Semiconductor, BICMOS: Bipolar Complementary Metal Oxide Semiconductor, Electronic Devices


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