This page provides a short discussion of IC Propagation delay [Tpd] and how it
varies as the environment or individual designs vary. Any numbers
provided to indicate changes in Propagation delay are general and only
used to show a relationship. Real Propagation delay numbers, or changes
in Propagation delay will depend on the logic family or device used.
There are dozens of different logic families, all with different
propagation delays, input load values, and other characteristics. The
point here is to show that if a circuit design requires the correct
characteristic to operate correctly, then these additional considerations
need to be accounted for. In general the propagation delay of an IC will
differ from what is shown in the data sheet because of one or more of the
changes in operational characteristics discussed below. However the data
sheet for a device may account for some of these changes [operational
temperature, Vcc variation], but usually not for increases in
Propagation delay may also be affected by the number of outputs switching
simultaneously. The 74FCTxx family adds an additional 250pS to the
Propagation delay for each output in a package switching [above the first
one]. The data sheet may be providing min/max Propagation delay for one
output switching or all possible outputs switching at once. If the device
has 8 or 16 outputs the Propagation delay could change by a large
One other factor which may increase Propagation delay could be induced by
adding a series termination resistor to reduce reflections on the line.
Line terminations are discussed on the Trace Termination page.
So if your asking why do I care about IC propagation delay or does IC output propagation delay effect may design, or how do changes in propagation delay effect my design then you may need to account for the variations already discussed.
Intermittent operation, or failures may be seen if the variation discussed above have not been accounted for. In the lab, the power supply was always re-adjusted [for each test] to provide the correct Vcc regardless of load, while the fielded board [PWB] does not. In the lab the temperature is always 25oC, the fielded board resides in a Humvee out in the desert. My test code pushed 2 data bits out this IC, but the real data switches all 8 bits. There were two boards [PWBs] in the test chassis while 4 boards reside in the operational chassis. If the minimum and maximum values for propagation delay is not accounted for then one board may work [having one delay] while another board with the same design may not work, because the propagation delay changed with the different chip used. Propagation delay will change from IC to IC between the listed minimum and maximum values listed on the data sheet.
The issue is a problem but may not show as a failure for all fielded boards, or for boards fielded to a particular region, or it will just show as a random error with no correlation. So the rule is; follow the design rules for the particular logic family used or after the fact [once the design is done] determine what is causing the random errors [which is much harder]. Account for the propagation delay changing between the minimum and maximum values provided in the data sheet, then account for another other issue which may tend to increase the propagation delay. Don't rely on a typical value with out accounting for the variation between minimum and maximum values. Intermittent circuit operation may be seen when switching times are not accounted for.
How to design determine propagation delay within systems or interconnecting circuits.
Each component in the system adds propagation delay to the signal, not just the Integrated Circuit [IC].
The graphic above shows an example backplane interface, with slot 1 transmitting to slot 5 [blue transceivers].
The individual Printed Circuit Board [PCB] contains the transceiver IC, with a one inch trace [light blue] to the board connector, and then the physical connector itself [gray].
Each card is designed the same, with the ICs as close as possible to the backplane connector, 1 inch in this example.
The backplane connectors are spaced at a standard 0.8 inches between boards.
The 0.8 inch board-to-board spacing is common in a large number of backplane formats.
Because the two boards that are communicating are four slots apart, at the spacing defined, the backplane length is well defined [as shown].
Note that the Trace Propagation Delay is shown in blue text and the component load capacitance is in red text.
Circuit voltage termination [Vtt] is shown for completeness, but is not involved in the calculation.
Propagation Delay: 0.8 inches = 2.032cm ~ 0.137nS;
----- Trace Propagation Dealy = 1.0 inch = 2.54cm; Trace Lenght ~ 0.170nS;
----- Backplane Connector ~ 0.135nS
Total prop delay = 1.158nS [Driver to Receiver] = (0.137nS x 4 slots) + (0.17nS x 2 traces) + (0.135nS x 2 connectors)
Trace capacitance is 4.02pF/in [FR4 board material]
Total trace capacitance = 4.02pF x 5.2in = 20.9pF [PWB to PWB distance]
----- This figure changes with board material and outside or internal layer used. [Characteristics of Board Materials]
Total load capacitance = 88.9pF = 20.9pF + (8pF x 5) + (2.8pF x 2)x5 (10 times normal LVCMOS load)
---- Trace capacitance + IC capacitance + connector capacitance
Capacitance per unit load = 17.62pF = 8pF + (2.8pF x 2) + 4.02pF
----- IC output capacitance + connector capacitance
Zmin > 1 / [ 2 x 3.14 x 622MHz x 1.25 x d x Co] = 1 / [2 x 3.14 x 622MHz x 1.25 x 4.57cm x 17.62pF]
----- Minimum impedance
Skew: Connector 8pS/connector [assumes same row]; Backplane 25pS WAG; Board 10pS/board WAG
Total System Skew = 69pS = [8pS x 3] + 25pS + [10pS x 2]
Sample Window = 580pS [Altera data sheet]
TCCS; Channel-to-Channel Skew = 400pS [Altera data sheet, max, -1ver]
TUI; Timing Budget = 1.190nS [Altera data sheet, min, -1 ver]
RSKM = [TUI - SW -TCCS]/2 = [1.190 - 0.580nS - 0.400nS]/2 = 105pS
Margin = 26pS = RSKM - [clock jitter + System Skew] = 105pS - [10pS + 69pS]
CCA to CCA has a 1.158nS trip delay with a 26pS timing window
CCA to CCA adds another 1.158nS trip delay
Design Hint; Most backplane connector are multi-row devices.
So when doing the above equations be sure to stay within the same row of the connector, otherwise your calculations will be off.
The table above shows the difference in propagation delays depending on the row of pins used.
The higher the row on the [daughter card] connector the greater the propagation delay.
This would be for a right-angle board connector;
a straight connector found on the mother-board would have prop delay rates equal, because all the pins on a straight connector are equal length.
Switching Terms -
VCC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at.
VIH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high.
VIL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low.
VOL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level.
VOH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level.
VT: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.
Description of TTL, ECL and CMOS Glue Logic Families
|Standard Logic Voltage Thresholds||Interface Bus Logic Thresholds||Glue Logic Logic Speed x Power Chart||How to Termination Traces||Ground/Power Planes|
Back to the Logic Design Page, Also refer to the Delay Logic Manufacturers page.