Logic Input/Output Pull-up values

Logic Vol and Voh diagram [Voltage output-low vs Volatge Output-High]

Unused Input pins should be tied to a valid logic level so the input remains fixed at a valid voltage level. Unused inputs are susceptible to noise which could cause the output to switch.
Unused or floating inputs may "act" one way [as a logic 1] while they appear another when probed [as a logic 0 or invalid voltage] ~ which may lead to confusion during debug.
Normally the unused pin will be tied to Vcc or ground; however, they may also be tied to a used input of the same chip (if it happens to be a glue logic OR gate, or AND gate...}

To protect the input pin from transients on the Vcc line a Pull-up resistor should be used.
The exact value of the pull up resistor depends on a number of factors which are discussed below.
Designing in the wrong value of pull up resistor could actually cause the circuit to malfunction.
So use a pull-up resistor if you need one, but only if it's required.
For example, the AC/ACT logic families do not require a pull-up resistor on input pins [I/O pins differ].
Normally a pull-up resistor can be used with one or two pins as shown in the diagram.

Resistor Pull-up to Vcc of an Unused input pin

A floating state is defined when the voltage at a gate is determined by the leakage current of the device. Unused CMOS inputs which are left floating will experience a gradual charging of the gate input capacitance. A floating input may see an increase in static current, or if the gate voltage reaches the threshold level start to oscillate. Both the N and P FET outputs will turn on and conduct current simultaneously if the input to a CMOS device is allowed to float. Voltages between 0.8v and 2.0v applied to the inputs will cause a problem, in that the outputs will tend to oscillate. Large numbers of gates left floating, in a 16 bit bus driver for example, will cause large amounts of current to be drawn by the IC. The floating gate charges up at a rate determined by its leakage current. Intermittent or random circuit errors may be seen with floating inputs, as outputs switch to a different state for no apparent reason.

It's good design practice to tie the unused input to Vcc via a resistor to reduce noise susceptibility. The resistor protects the input pin by limiting the current from high going variations in Vcc which could damage the input to the device. The resistor value used as a pull-up may vary between logic families. The number of inputs allowed to be tied to the resistor pull-up also varies with logic families. In fact some device families really don't require a resistor at all. The [old] TTL emitter input logic families required the resistor, while newer TTL families may not because they could accept a higher break down voltage on the input pin [protected by Schottky diodes]. The resistor value does not change based on the protection provided, but by what the input pin requires as a valid logic level. A resistor value of 1K ohm to 5k ohms is common and should work for all logic families as a pull-up.

So determine if parts count or cost come into play with this design, are you building 3 prototypes or 10,000 units [to determine the cost and impact of the resistor]. Next determine if the resistor is really required, check the IC logic family being used, it may or may not require a pull-up resistor.
If you do need resistor pull-ups, next determine if you should use an individual Resistor, or a Resistor Array. Also Resistor Array Schematics.

Calculate the pull up resistor value: [example CMOS values used]
(1) Check IIH {or maybe just II for same devices}, Input High Current on the data sheet. [10uA]
.....{1a} Use the maximum current value if provided. [20uA]
{2} Determine the input voltage to tie into, normally Vcc, or VIO. [3.3v]
....{2a} Use the minimum voltage value if provided. [3.1v]
{3} Select the resistor tolerance family, which is already being used in the design. [1%]
{4} Check the minimum input high voltage VIH for the device, from the data sheet. [1.8v]
....{4a} Use the maximum value as good design practice [2.52v]
....{4b} Using the minimum results in a loss of noise margin, and absolute worst case, not to exceed value
{5} Calculate the Pull-Up Resistor: Rpull-up
....{5a}Keep the voltage drop {VResistor x IIH} from dropping the VIH below minimum.
....{5b} Use the maximum value in the calculation as good design practice [2.52v]. The equation is listed below.
        VIH Vcc [min] - {VResistor [min] x IIH [max]}
        1.8v VIH-Min 3.1v - {1k x 20uA} = 3.1v - 0.02 = 3.08 {This works}
        1.8v VIH-Min 3.1v - {47k x 20uA} = 3.1v - 0.94 = 2.16 {This works, but produces a loss of noise margin of 0.8v}
        2.52v VIH-Max 3.1v - {1k x 20uA} = 3.1v - 0.02 = 3.08 {This works}
        2.52v VIH-Max 3.1v - {22k x 20uA} = 3.1v - 0.44 = 2.66 {This works, without a loss in noise margin, see below for slow input voltage rise time}
Note: The example uses 10uA (20uA worst case) for gate leakage current. For any gate, Leakage current doubles for each 10oC increase in temperature above the data sheet (25oC)
....{5c} Use this equation for CMOS inputs which may tend to oscillate with slow rise times.
        Vt = VCC - [e-t/RCT(VCC - Vi]    Describe under the Tri-State section below

The point to remember is that the design should function under worst case conditions. It's just a pull-up resistor, don't install a value which could hurt the circuit operation, otherwise the pin should have been taken directly to Vcc without the resistor [which always works]. Use the worst case values:
     Vcc: minimum value expected
     VIH: maximum value expected
     RPull-Up: maximum value expected [the value chosen plus the 1% or 5% tolerance variation]
     IIH: maximum value expected {Add each additional pin pulled up by a single resistor [20uA + 20uA for 2 pins pulled up]
If you have a noise budget; [example numbers provided]
Subtract another 0.4v off Vcc minimum to account for ground bounce. [3.1v - 0.4v = 2.7v]
Subtract another 0.1v off Vcc minimum to account for noise on Vcc. [2.7v - 0.1v = 2.6v]

A diode may be used instead of using a resistor for a pull-up. When a diode is used it's called "clamping". The device's input pin is connected to a resistor to ground and two diodes to Vcc. The input pin is then tied [or clamped] to 2 diode drops [1.4v] below Vcc. This method protects the input pin just as the pull up resistor does; however, no one would use this because it requires 3 parts instead of one pull-up resistor. So I offer no calculation for the values.

Calculate the minimum load a device can safety drive:
For a low-to-high transition, the equation is;
     ZLH = [(VOH (min) - VOL {typ)) / IOH
For a high-to-low transition, the equation is;
     ZHL = [(VOH (typ) - VOL {max)) / IOH

Slow Rise Time Definition

What to do with Tri-State Output pins

Open Collector Output pins should be tied to a valid logic level so the output remains fixed at a valid voltage level when the device turns off. Wire AND-ing requires a resistor pull-up which needs to function for the range of devices tied to the wire-AND. The minimum value of pull-up is calculated while only one output is low, the maximum value of pull-up is calculated while all outputs are high. Both equations are listed below:

RPull-Up {min} = ( [Vcc {max} - VOL] / [IOL - NumInput Unit Loads {Low} * IIL] )

RPull-Up {max} = ( [Vcc {min} - VOH] / [IOH * NumOutput Unit Loads + NumInput Unit Loads {High} * IIH] )

NumInput Unit Loads {Low} = the number of input devices connected to the wired-OR
NumOutput Unit Loads = the number of Open Collector devices connected together

IC devices use Open Collector outputs for a number of reasons:
... Wiring AND-ing two or more Open Collector device outputs together
... Allowing the device to drive another type of device at a different Vcc.

Bus-Hold Input Pins, Pull-up resistors should not be used with an IC that has Bus-Hold. Bus-Hold Input Pins Discussion

Terms -
VCC: The voltage applied to the power pin(s). In most cases the voltage the device needs to operate at.
VIH: [Voltage Input High] The minimum positive voltage applied to the input which will be accepted by the device as a logic high.
VIL: [Voltage Input Low] The maximum positive voltage applied to the input which will be accepted by the device as a logic low.
VOL: [Voltage Output Low] The maximum positive voltage from an output which the device considers will be accepted as the maximum positive low level.
VOH: [Voltage Output High] The maximum positive voltage from an output which the device considers will be accepted as the minimum positive high level.
VT: [Threshold Voltage] The voltage applied to a device which is "transition-Operated", which cause the device to switch. May also be listed as a '+' or '-' value.

Description of TTL, ECL and CMOS Glue Logic Families

Related pages on this site:
. Standard Logic Voltage Thresholds . . Bus Logic Thresholds . . Logic Speed x Power Chart . . Trace Termination . . Resistor Definitions .

Back to the Logic Design Page.

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Modified 6/13/15
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