I²S Bus (IIS, or I2S) is a serial bus designed for digital audio devices. The I2S design handles audio data separately from clock signals. An I2S bus design consists of three serial bus lines: a line with two time-division multiplexing (TDM) data channels [SD], a word select line [WS], and a clock line [SCK].
Data is transmitted two's complement, MSB first. Data sent from the transmitter may be synchronized with either the high-to-low or low-to-high transition of the clock [SCK], but the receiver latches the data on the leading edge of the clock. The word select line [WS] indicates which channel is being transmitted; Channel 1 WS = 0, or channel 2 WS = 0. The I²S Bus uses standard TTL logic levels. Typical clock [SCK] frequency is 2.5MHz, maximum clock speed is 3.125MHz. The WS line is sent one clock before the data is sent.

One chip in the I²S Bus system generates a Master clock, while all other devices derive their internal clocks from this reference. Standard clock rates include: 32KHz, 44.1KHz, or 48KHz [or multiples of these]. Data may be sent MSB first or LSB first. The word length is adjustable up to 28 bits. Synchronization with the data words may also be set to either the rising or falling edge of the clock. The Master drives SCK, and WS. Either the Transmitter, Receiver, or Controller may be the Master. The I2S bus turns up on Stereo CODEC's, DAC's or micro-processors. The I²S Bus was developed by Philips in 1986 as a 3-wire bus.