I2C Bus

[I2C Bus Description]
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I2C Bus Description

I2C bus was developed by Philips Semiconductors [NXP], originally designed to be a battery control interface.
The I2C interface standard defines both the electrical layer and protocol layer.
The I2C bus uses a bi-directional Serial Clock Line [SCL] and Serial Data Lines [SDA]. Both the SCL and SDA lines are pulled high via an Rp resistor. Resistor Rs is optional, and used for ESD protection for 'Hot-Swap' devices. No other lines are specified. Any device may be a Transmitter or Receiver, and a Master or Slave. Data and clock are sent from the Master ~ valid while the clock line is high. The link may have multiple Masters and Slaves on the bus, but only one Master may be active at any one time. I2C Slaves may receive or transmit data to the master.

I2C Bus Interface Circuit
I2C Interface Circuit Schematic Diagram

I2C Bus Speed

There are a number of speed grades available depending on the I2C interface specification version
Three speed modes are specified in the 2001 I2C standard version:
Standard; 100kbps [Bits per Second], Fast mode; 400kbps, and High speed mode 3.4Mbps [HS Mode].
While the 2006 I2C version defines the Fast Mode Plus speed grade which increase the bus speed to 1MBps [1MHz].

I2C Communication

I2C, due to its two-wire nature (one clock, one data) can only communicate half-duplex. The maximum bus capacitance is 400pF, which sets the maximum number of devices on the I2C bus and the maximum line length. The interface uses 8 bit long bytes, MSB [Most Significant Bit] first, with each device having a unique address.

Data on the SDA data line only changes when the clock line [SCL] is low. However if SDA drops while SCL is high a start of frame is indicated. Also if SDA rises while SCL is high than a stop condition is indicated. The Start condition indicates a start of frame and the Stop condition indicates an end of frame. Each transfer on the I2C is 9 bits long, eight data bits followed by a '1' bit. The listener acknowledges the receipt of the byte in one of two ways; the listener may over write the '1' bit with a '0' bit indicating ready for more data. or leaving the trailing '1' indicating not ready for data.

The Master [talker] always generates the clock and the message. An I2C message begins with a Start bit, followed by a 7 bit Slave address and then a direction bit ['1' for Read, '0' for Write]. Once the slave address is sent, the slave is required to respond, otherwise the master will send a Stop or Retry bit.
If the Master sends a Write bit, the master will follow that with a sub-address to indicate a particular register. The slave will stop acknowledging the last byte of the transfer.

Remember that the I2C bus is defined as having a maximum capacitance of 400pF, that defines the maximum number of I2C components on the I2C bus and the I2C length [in combination]. So the I2C Bus length is never defined in the I2C Bus specification. However, there is one note in the interface specification: If the length of the bus lines on a PCB or ribbon cable exceeds 10 cm and includes the VDD and VSS lines, the wiring pattern must be: SDA - [Power/Ground or Ground] - SCL, or no Vdd/Vss lines if there embedded within the PCB.
Of course this could also be a twisted pair or shielded cable but I2C cable length still depends on the type of cable [and its capacitance] and the number of I2C devices.
Each I2C device is defined to have 10pF per I/O pin [maximum].

I2C Bus Voltage Levels

The voltage VDD may be different for each device, but all devices have to relate their output levels to the voltage produced by the pull-up resistors [RP] It is possible to run off two different bus voltages, but they have to be translated [refer to the spec.]. The I2C serial interface above show the I2C Pull-Up connecting to Vdd [supply voltage].

I2C Bus Terms

The I2C bus may also be seen as the Inter-IC Bus or the IIC Bus which all mean the same thing. The most common term is of course I2C. Of course there are always other references; I2C Serial Port, I2C Digital Interface, I2C Interface or I2C Interface Specification.

I2C Bus Interface IC Manufacturers

Analog Devices
{12-Bit Plus Sign Temperature Sensors with SMBus/I2C-Compatible Serial Interface}

{10-Bit Temperature Sensors with I2C-Compatible Serial Interface, Digital Potentiometer}

NXP Semiconductors
{ICs with an I2C Bus}

Many ICs have the I2C interface including;
processors, controllers, GPIO Expanders, LCD Controllers, Temperature Sensors, and Bus Controllers.

IC Manufacturers {All types, or use the Components Icon below}

{I2C Bus Index}

I2C Bus Standards Information

The I2C Interface Specification may be down loaded from NXP [new name for Philips Semiconductor]
The I2C-Bus Specification, Version 2.1, January 2000; {Philips Semiconductor}
The above standard contains the Standard-Mode, Fast-Mode, and High Speed Mode [HS] upgrades.
The latest I2C revision; Fast Mode Plus [fm+] was released in April 2006
Previous Standards Revisions; I2C Version 1.0, 1992. I2C Version 2.0, 1998.
The I2C interface specification was developed by Philips Semiconductor

{Back to I2C Bus Index}

Access Bus Description

Access.Bus is a low speed serial bus that was aimed at the PC market.
Access.Bus uses the I2C bus as the electrical hardware interface.
A four pin modular type connector and a shielded 4 wire cable is called out in the specification.
ACCESS.bus operates at 100 Kbps with a maximum cable length is 10 meters.
Access.Bus uses the same signals as the I2C bus, and adds ground and power for the cable.
Refer to the main Access Bus page for more information on this interface bus, including pin outs and signal assignments.

PC motherboard

Distributor rolodex Electronic Components Electronic Equipment EDA CDROM Software Engineering Standards, BOB card Cabled Computer Bus Electronic Engineering Design Table Conversion DB9-to-DB25.
DistributorsComponents Equipment Software Standards Buses Design Reference

Modified 1/19/12

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