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Sample and Hold

A Sample and Hold circuit holds a sample of a signal for a short amount of time.

Sample and Hold Circuit
Sample and Hold Circuit

This example of a Sample and Hold circuit uses two Operational Amplifiers [Op Amp] as buffers. The first Op Amp drives the Analog Switch, while the second Op Amp buffers the 'Hold' capacitor from the circuit beyond.
A Control signal [usually digital] operates the analog switch by opening and closing the switch as required. When the switch is closed the capacitor samples the incoming signal, by charging up to the voltage level of that signal. Once the signal is captured [capacitor is charged], the switch is opened and the capacitor 'Holds' that voltage level.
Some other circuit, not shown, then uses or stores the voltage level for some purpose.

There are a number of design issues that come into play when working with a Sample and Hold circuit; including pulse timing, and sample precision. Because of leakage, the capacitor is only able to hold a voltage level for so long. As time progresses the voltage held by the capacitor will fall. The voltage on the capacitor will decay or Droop as determined by the leakage current flow into or out of the capacitor. Droop Rate is the term used to describe the capacitors ability to hold a voltage.
The analog switch needs to be held open until the capacitor is discharge other wise the next voltage sample may be the addition of the new level and part of the previous voltage level. However the switch also needs to be held closed to give the capacitor time to charge up to the voltage level being samples.

The charging rate [Rise Time] of the capacitor is the addition of the output resistance of the first buffer and the 'On' resistance of the analog switch, times the value of the capacitor.

Sample and Hold Logic Diagram
Sample and Hold IC

IC Notes;
The external hold capacitor should be either Teflon or polystyrene so that dielectric absorption is minimized. This will insure that excessive sag back after capacitor sample mode charging does not occur. Hold step is sensitive to stray capacitance coupling between input logic signals and the hold capacitor.

Hold mode leakage current is actually JFET junction leakage current which doubles (approximately) for each 10C increase in junction temperature.

A possible test circuit would be to continually sample the output of the sample and hold circuit, to determine if the output varies outside the expected tolerance. The important criteria this circuit is to hold the vale that was sampled.

Any IC package is possible, but only an 8-lead metal can is shown as an example [TO-39]. However an 8 lead DIP package or SOIC might be more common.

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