FastBus Interface

FastBus Description

IEEE Std 960-1993 Defines the Mechanical, Electrical, and Protocol. The link indicates a 32 bit ECL interface for data and address buses.
ECL IC manufacturers are listed on the Standard Logic Manufacturers page.
Fastbus was released in 1986, while the current version dates to 1993, which would be obsolete.

"FASTBUS is a sophisticated data acquisition system standard developed by the U.S. NIM Committee in collaboration with the European ESONE Committee (ANSI/IEEE STD 960-1986).
FASTBUS was designed to keep features of older important standards while extending the capabilities of data acquisition systems.
FASTBUS provides for a more densely packed system, reducing dramatically the per-input cost. This and other design goals have been achieved.
A standard rack-mountable crate had 26 slots. The backplane used asynchronous ECL signals.
FASTBUS meets the requirements of the next generation of data acquisition systems by incorporating several powerful features, including:

Modularity
32-bit address and data fields
High speed, asynchronous ECL backplane with a 32-bit wide data-way
Multiple, parallel processor bus architecture with multiple bus segments that operate independently but link together for passing data
Asynchronous handshaking for compatibility with modules having different data transfer speeds operating on the same bus
Synchronous non-handshake data transfer for maximum speed
Broadcast operations for initializing, clearing, etc., several modules in one operation
A polling structure for fast scanning of sparse data from a large number of modules
Easy links to computers for Host intervention or data transfer

Essentially, the FASTBUS backplane is intended to be an extension of a computer backplane. By its nature, therefore, it is an expandable system. The backplane is called a "Segment". Connections between segments are made by an interface, called a Segment Interconnect (SI). An SI in one segment is connected to a SI in another segment by a Cable Segment. The Segment Interconnect can be either a Master or Slave, depending on the operation it is performing. Moreover, it can be a Master on the FASTBUS Segment and simultaneously a Slave on the Cable Segment. The designations Master and Slave here are dynamic, in that the designation is defined by the role played by the SI at some given time.

FASTBUS permits multiple masters to have access to the segment. The standard provides a protocol for arbitration when more than one master requests control of the segment. Once mastership is granted, the Master may then proceed to establish a communications "lock" with any other device on the segment which will act as a Slave. Alternatively, the Master may broadcast a message to all Slaves which respond to the broadcast (e.g., clear, polling for data ready, etc.).

The integrity of communication between Master and Slave modules is ensured via a handshaking scheme. Refer to the Definition of Handshaking. This frees the standard from a speed requirement. That is, communication occurs at whatever speed the Master/Slave system will support. This, of course, is not the case with broadcast commands where a Master talks to all Slaves in a segment, nor is it true for hardware block transfers where the Master must be able to operate as fast as the fastest Slave. So while there are cautions required for use of FASTBUS, the versatility and expandability is sufficient to meet the most demanding requirements of data acquisition systems." extracted from: An Introduction to FASTBUS {fermilab}. The author of this page has not reviewed the Fastbus specification.

There is no up-grade path for FastBus users.
That is, there is nothing to purchase to upgrade the interface.
Either a custom interface needs to be designed or a completely new system needs to be used.


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