Leroy Davis
1890 Crane Creek Blvd
Melbourne, FL 32940
ph: (321) 757-3727
interfacebus.com@gmail.com
http://www.interfacebus.com/
OBJECTIVE: Team Lead, System Specifications, Board Designer, FPGA Designer
EDUCATION:
B.S. Degree in Electrical Engineering Technology, May 1984: Old Dominion University, Norfolk, Virginia
EMPLOYMENT:
Harris Corporation, Melbourne Florida, May 5 1997 - Present
Current position; Lead Board Designer, 14 layer OTN card
Designed 14 Layer PWB,with 7 FPGA [not the designer], running 66MHz clocks.
Lead Hardware Engineer, on a multi-chassis (VME), Radar Simulator.
Supervised the redesign of 2 PWBs and 3 FPGAs, and the documentation.
Supervised the design of 1 Circuit design/PWB and 1 FPGA, and the documentation.
Supervised a number of Engineers and Technicians
Generated or Supervised a number of CDRs and PDRs [Critical Design Reviews]
Produced specifications defining 4 separate 21 slot VME chassis.
Designed a Xilinx 4005 FPGA using VHDL and Synopsis, to control data I/O into a FIFO.
Designed a Xilinx 4013 FPGA in VHDL which controlled a number of devices.
Redesigned an Altera PLD, using Altera's MAXPlus2.
Developed a Printed Wiring Board using Cadence schematic capture.
Wrote a number of Hardware Description Specifications (HDS), for PWBs and FPGAs
Alliant Tech Systems, Annapolis Maryland, October 2 1995 - April 25 1997
Designed an ‘Altera’ FPGA to enable automatic signal routing for a product test set.
Designed an ‘Altera’ FPGA using both AHDL and schematic entry, simulation using the MAXPlus2.
Produced a PC104 extension PWB, for testing {one-for-one pin connections}
Worked with Printed Wiring Board vendors implementing IPC-RB-276 specifications.
Investigated different modifications to lap-top PCs, for rugged-ized operation, centered around the ATA spec.
System Engineering on a VME/RaceWay based Radar Simulator, UNIX operating system.
Supervised the modification and layout of a number of PC boards.
HRB SYSTEMS, Stafford Virginia, July 9 1990 - June 4 1995
Designed a Memory card (VME form factor) with automatic recycle capability.
Designed a Synchro to Digital converter card to control an antenna pedestal.
Designed a VME interface card with BLock Transfer (BLT) capability, using 22V10 PLDs, with ABEL.
Designed a 200MHz Time of Arrival card, using the ECLinPS series of ECL.
Designed an asynchronous DRV11WA (uVAX) to HP FIFO interface card.
Designed a Memory card with DMA, controlled by a DRV11J and interfacing to a DRV11WA (uVAX).
Designed a 20MHz Memory / FIFO card with DMA capability to a DRV11WA (uVAX).
Designed a 20MHz A/D converter card interfacing to a custom backplane.
Wrote a number of Interface Control Documents (ICD) specifying current system configuration
National Security Agency, Ft Meade Maryland, September 23 1985 - July 6 1990
Worked in the secure communications area, designing and evaluating secure voice equipment, and detection equipment.
Designed the black section of a 10 channel STU III automatic digital conferencer, which interfaced to the public phone system, the design included
a 8051 micro-controller programmed in C.
Designed a 100MHz (delay and multiple) chip rate detector, using both 10KH ECL and AS TTL devices.
Designed an IEEE-488, GPIB standard (listen only) interface with DMA capability.
Designed and wire-wrapped a 20MHz 16 to 32 bit comparator circuit to flag bus errors.
Designed a 20MHz D/A converter to test an in house digitizer.
Evaluated new equipment and signal analysis software routines.
Performed market surveys to up-date and replace existing hardware.
Pulse Communications, Herdon, Virginia May 14 1984 - September 17 1985
Worked in the digital telephone area developing voice grade transmission (2 to 4 wire) modules, interfacing to a T1 link.
Designed, prototyped, and tested various D4 channel bank cards.
Design responsibilities included accepting a concept from the marking department, setting up a design schedule, and generating test specifications.
Interacted with other departments to oversee component acquisition, schematic generation, PC board layout, and production testing.
Introduced two (redesigned) products into the market place.
Generated test specifications.
Security Clearance:
TS/SCI SBI: 01/10/04 ~ active, HISTORY: TS/SBI: 01/xx/03, TS: xx/xx/98, TS/SCI: 07/26/91, TS/SBI: 11/30/85,