# Glue Logic IC Timing

All logic devices have a typical propagation delay. The propagation delay is the amount of time it take the devices output to respond based on a change to the devices input. The delay is given for a particular power supply voltage at a certain ambient temperature with some load. As the temperature and or load [current demand] increase, the propagation delay will increase. A variation in power supply voltage will also change the propagation delay, but the change [either up or down] will depend on the device being used. Device data sheets will normally provide a minimum and maximum propagation delay.
The variation accounts for operation temperature range changes, power supply variation and so on.

It's common for an IC to have one propagation delay when switching from high to low and a different propagation delay when switching from low to high.

Chart of Glue Logic Truth Tables; AND Gate, NOR Gate, OR Gate, Exclusive OR Gate, NAND Gate, Exclusive NOR Gate, and the NOT Gate.

In this case, the first figure shows a 3nS [10-9] propagation delay. Three nano-seconds after the input switches high the out put switches high. The example trace uses a 8nS high pulse followed a 14nS low pulse. Refer to the Speed vs Power chart for typical propagation times for each of the standard glue logic families.

The typical delay is what can be expected in most cases. How ever; the device really has a minimum and maximum delay. In many cases [only] the min. and max. propagation delay is provided in the data sheet. The minimum propagation delay shown below is 1nS, the maximum propagation delay shown is 4nS. These propagation times will change with different devices in the same logic family and will vary widely between different logic families.

The combination of the minimum and maximum propagation delay results in a timing ambiguity shown has hash marks rather than straight [0ns] rise times. Output 'Y' may change 1nS after input 'A' or it may take up to 4nS for output 'Y' to change. Normally once the device is installed onto a circuit board the delay is fixed at a value determined by the natural delay of the device and the load connected to it. However changing the ambient temperature or varying the supply voltage will cause the signal delay to slightly increase or decrease. If the same circuit is used with another identical IC, the signal delay will differ with the chip and the change in load resistance.

Timing ambiguity adds. So with both 'A' and 'B' inputs arriving with a 1nS difference [ambiguity], the output ambiguity increases by 1nS. This results in an output that may have a pulse which may be longer or shorter then either of the incoming pulses. The figure depicting a four input AND gate [below] shows the result of signals arriving at different times. Of course no runt pulse would occur when the high period of the pulse is much greater then the rise time of the signal

Another view below, depicts each of the four inputs arriving at different times. A runt pulse is possible if the time delays between pulses are off-set by a few nanoseconds, which is a large percentage of the [high] pulse times. The circuits below use an AND gate, but any gate produces the same effect.

The next gate following the 'Y' circuit may not function with the runt pulse as an input. Or if the pulse is the input to a Flip Flop, the clock may not arrive at the correct time to capture the logic value.

Timing ambiguity between the data and clock into a Flip Flop may produce oscillations on the output, refer to the Digital Logic metastability page for a description.
Timing ambiguity in AND / OR gate logic may also produce glitches, refer to the Glue Logic Timing Hazards page for a description.

For other logic issues see the Design icon at the bottom of the page, for logic design pit-falls and other issues.

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Modified 3/05/12