CompactPCI P1 Pinout

cPCI Introduction:

The CompactPCI pinout for P1 [J1] is provided below. cPCI is electrically identical to the PCI specification, it uses the same signals.
However some signals have been added to the cPCI standard in addition to what the PCI specification called out.
cPCI uses pin/socket connectors, while PCI uses Finger/slot connectors.
A # symbol at the end of a signal name indicates that the signal’s asserted state occurs when it is at a low voltage.
The absence of a # symbol indicates that the signal is asserted at a high voltage. The pin descriptions which indicate a Key is not a pin, but a male or female void [key].
The V(I/O) pins are un-named in this table. In a +5 volt system the V(I/O) pins are +5volts, in a +3.3 volt system the V(I/O) pins are +3.3 volts.
The pin out for the P2 connector is listed on the cPCI P2 Pinout page.

Note that some of the pin names have been combined into a single column, however the individual pins are still there.
These P1 signals are referenced to the removable card, the backplane side would use the J1 term [for the same connector].

Connector Mechanical Definitions:

cPCI uses 2mm 'Hard Metric'; IEC 1076-4-101, a number of different pin arrangements. Normally the outside Ground rows (which are compression pins) 'Z' and 'F' are not counted as pins. OEM pin numbering may be by cPCI or in accordance with IEC 61076-4-101 (which is reversed). The term "Hard Metric" only means that metric dimensions are preferred ~ with-out regard to inches.

cPCI 2mm connectors mating distances [12.50mm] matches the 96 pin DIN 41612 connectors used with other EuroCard packaging [IEC 273 or IEEE 1101, 1101.10], like VMEbus. FutureBus connectors which also use 2mm style have a mating distance of 10mm, and are not compatible with cPCI connectors.

The connector types below are counting signal pins (not the ground rows), as indicated on many data sheets:

Type A connector; 110 pins, Keyed (J1/J4),([25 rows x 5 columns] - [3 rows x 5 columns of Key])
Type B connector; 110 pins (J2/J5), [22 x 5]
Type B connector; 95 pins (J3), [19 x 5]. This is also used as P0 with VME64
Type C connector; 55 pins [11 x 5]
Type AB connector; 95, 110, or 125 pins

There are other types:
Type L connector; # contact cavities to accept power insert contacts
Type M connector; # contact cavities to accept power insert contacts/with half the connector having normal pins

Signal Definitions:

AD[31::00] [Tri-state] Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an address phase followed by one or more data phases. The Time Multiplexed Address and Data bus may exist as either 0 to 31 bits (32bits) or 0 to 63 bits (64bits) using the 64 bit expansion bus. Both the Address and Data line use the same bus, Address first then Data. 32 bit PCI may also use 64 bit addressing by using two address cycles; termed Dual Address Cycles (DAC), the low order address is sent first. Additional control bits are utilized once the bus is increased to 64 bits.

REQ# [Tri-state] Request indicates to the arbiter that this agent desires use of the bus. This is a point-to-point signal. Every master has its own REQ#.

TRDY# [Sustained Tri-State] Target Ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. TRDY# is used in conjunction with IRDY#.

STOP# [Sustained Tri-State] Stop indicates the current target is requesting the master to stop the current transaction.

LOCK# [Sustained Tri-State] Lock indicates an atomic operation to a bridge that may require multiple transactions to complete. When LOCK# is asserted, non-exclusive transactions may proceed to a bridge that is not currently locked.

M66EN [Input signal] The 66MHZ_ENABLE pin indicates to a device whether the bus segment is operating at 66MHz or 33 MHz.

PAR [Tri-state] Parity is even parity across AD[31::00] and C/BE[3::0]#. Parity generation is required by all PCI agents. PAR is stable and valid one clock after each address phase.

SERR# [Open Drain] System Error is for reporting address parity errors, data parity errors on the Special Cycle command, or any other system error.

C/BE[3::0]# [Tri-state] Bus Command and Byte Enables are multiplexed on the same PCI pins. During the address phase of a transaction, C/BE[3::0]# define the bus command.

DEVSEL# [Sustained Tri-State Output] Device Select, when actively driven, DEVSEL indicates that the driving device has decoded its address as the target of the current access.

INT# [Open Drain] Interrupts on PCI are optional and are level sensitive, asserted low to signal an interrupt. However because these signals are not required, they do not have to be driven. There are four different interrupt lines.
--- INTA#, INTB#, INTC#, INTD#

GNT# [Tri-state] Grant indicates to the agent that access to the bus has been granted. This is a point-to-point signal. Every master has its own GNT#

IDSEL [Input signal] Initialization Device Select is used as a chip select during configuration read and write transactions.

Back to the main CompactPCI [cPCI] page, which contain a description of the bus, connector manufacturers, and IC manufacturer links.

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