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The three Trigger diagrams below reference the types of triggers that may be found on the VXI bus. The first diagram references an ECL trigger [ECLTRG] signal, while the next two figures reference TTL trigger [TTLTRG] signals. Each timing diagram details the setup and hold timings. The main VXI page is listed on the VXI Bus page.

ECLTRG [ASYNC] Trigger Protocol TTLTRG* [ASYNC] Trigger Protocol TTLTRG* Data Transmission Using Falling or Rising Edge Triggers

The figures above describe the timing for the VXI bus trigger signals. A logic high [1] is defined by a 2.0 volt level, A logic low [0] is defined by a 0.8 volt level.
All switching times provided are minimum.
Back to the main VXI Bus, or VME Bus page.

Engineering Key Words: VXI Timing, VXI-Bus, VME {Versa Module Europa} Extension for Instrumentation, VME, VMEbus, VME64, IEEE 1014-1987, Euro-Card size, Embedded Computer bus, VXI bus TTL Synchronous / Asynchronous Trigger timing, ECL Trigger timing, Interface Bus, Logic Level, Chassis Bus, Backplane, Interface, Trigger

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