VXI Bus Triggers

VXI Interface Timing
The three Trigger diagrams below reference the types of triggers that may be found on the VXI bus.
The first diagram references an ECL trigger [ECLTRG] signal, while the next two figures reference TTL trigger [TTLTRG] signals.
Each timing diagram details the setup and hold timings. Note that most values given are minimum times.
The VXI Bus page contains a description of the VXI interface.
The signal identified as the source of course is being driven by the source card.
The acceptor signal comes from the card receiving the signal.

ECL Trigger Protocol [Asynchronous Timing]
Voltage levels are Emitter Coupled Logic, at -5.2 volts and zero volts.

VXI bus ECL Trigger timing Diagram
[ASYNC] Trigger Protocol

TTL Trigger Protocol [Asynchronous Timing]
Voltage levels are Transistor-Transistor levels, at +5 volts and zero volts.
Note these are standard TTL levels, not Low Voltage [LVTTL] switching levels.
The notations indicate standard switching levels at 2 volts for a high and 0.8 volts for a low level.

VXI bus Asynchronous TTL Trigger timing
[ASYNC] Trigger Protocol

TTL Trigger Protocol using a clock signal [Synchronous Timing]
Data is assumed to be valid high or low as shown, the 'x' indicates invalid data [changing data].
Note the difference in timing between the rising or falling edge of the trigger.

VXI bus TTL Synchronous Trigger timing
Data Transmission
Using Falling or Rising Edge Triggers

The figures above describe the timing for the VXI bus trigger signals.
A logic high [1] is defined by a 2.0 volt level, A logic low [0] is defined by a 0.8 volt level for the TTL signals.
The ECL triggers, of course, switch at ECL logic levels.
All switching times provided are minimum [in nano seconds].

This data is based on revision 1.3 of the VXI specification [from 1987 if I remember correctly].
Although uncommon, a new standard could indicate different switching times of voltages.
VXI is an embedded backplane standard, and not used for consumer purposes.
Most of the signals defined under the VXI specification are identical to the VME specification.
The differences, that is the trigger signals are shown here. Other signal timing is provided on the VME page.

Back to the main VXI Bus, or VME Bus page.

Also Engineering Home > Interface Buses > Backplane Buses > VXI Interface > Trigger Signals.

Editor Note: The original VXI specification was based on the original VME specification.
The VME specification has since gone through a number of upgrades over the years.
There does not appear to be any evidence that the VXI standard has been up-graded over the years.
That is, none on the internet; however the specification was upgraded twice, once in 1998 and again in 2004.
Although the VXI standard does appear to be valid, but still locked to the original release of the standard.

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Modified 3/05/12
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