The table below lists the signal assignments for the P3 connector on the
VXI bus.
Only 9U high VXI boards will use the P3 connector.
Pinouts are provided for both the slot 0 card and slots 1 to 12 cards.
The VXI interface uses DIN 41612 connectors.
Companies that manufacturer DIN style connectors may be
found on the VMEbus page.
Slot 0 represents the system slot, while the other slots are used for regular card functions.
The two tables above list the VXI P3 connector pin-outs and signal names.
The connector is a 96 pin DIN (41612) 3 rows x 32 pins @ IEEE 1014-1987.
The first table defines the pin-out for Slot 0, the second table
describes the VXI P3 pin-out for all other slots. The differences between
VXI and VME {VXI P3 additions} are listed below:
CLK100: 100MHz differential ECL Clock; Sourced from Slot 0 and bused
to slots 1 to 12 on P3. Buffering occurs on the back plane, with each
slot appearing as a single destination (individually buffered).
SYNC100: Bused to slots 1 to 12 on P3. Buffering occurs on the
back plane, with each slot appearing as a single destination
(individually buffered).
ECLTRG2-5: ECL single ended 50 ohm Trigger Lines; Any module may
drive or receive these lines. Also refer to Timing for the VXI Trigger Signals..
Used for intermodule timing. Identical to
lines 0 and 1 on the P2 bus.
LBUS12-35: Local Bus, Daisy chained keyed bus; may be either ECL
or TTL. The signals are bused between adjacent slots only, I believe the keyed position
determines if two adjacent cards will talk to one another [Identical to
P2 Local Bus Lines].
Back to the main VXI bus page for VXI bus descriptions,
or VXI P1 connector pin-outs or VXI P2 connector pin-outs.
The VME bus Interface description is listed on the VMEbus page.
Recall that P3 connectors are only used in 9U systems.
VXI systems are not very common, and large 9U chassis are even less common.
Site Navigation: Engineering Home > Interface Buses > Backplane Interface Standards > VXI Board Standard > VXI Board J3 Signal Assignments.
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