VXI P2 Connector Pinout

The tables below list the signal assignments for the P2 connector on the VXI bus.
Pinouts are provided for both the slot 0 card [first table] and slots 1 to 12 [second table].
The VXI interface uses DIN 41612 connectors. Female connectors on the back plane, male style on the board side.
A listing of manufacturers which produce DIN 41612 connectors may be found on the VME page; a link is provided below the pin out table.

P2 Slot 0 PinoutP2 Slot 1 Pinout

Slot 0 represent the system controller, or bus controller.

The two tables above list the VXI P2 connector pin-outs and signal names. The connector is a 96 pin DIN (41612) 3 rows x 32 pins @ IEEE 1014-1987. The first table defines the pin-outs for Slot 0, the second table describes the VXI P2 pin-outs for all other slots. The differences between VXI and VME {VXI P2 additions} are listed below:

CLK10: 10MHz differential ECL Clock; Sourced from Slot 0 bused to slots 1 to 12 on P2. Buffering occurs on the back plane, with each slot appearing as a single destination (individually buffered).

TTLTRG0-7*: TTL Trigger Lines; Open Collector TTL lines used for intermodule communication. Any module may drive or receive these lines.

ECLTRG0-1: ECL single ended 50 ohm Trigger Lines; Any module may drive or receive these lines. Used for intermodule timing.

LBUS00-11: Local Bus, Daisy chained keyed bus; may be either ECL or TTL. Bused between adjacent slot only, I believe the keyed position determines if two adjacent cards will talk to one another.

The VMEbus Address and Data signals require 3-State drivers and receivers:
[A01 - A31], and [D00 - D31].

Timing for the VXI Trigger Signals are shown on another page.

Back to the main VXI bus page for VXI bus descriptions, or VXI P1 connector pin-outs or VXI P3 connector pinout.
The VME bus Interface description is listed on the VMEbus page.

Note Signal assignments and pinouts mean the same thing, each providing pin numbers and signal names and function.

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Modified 3/05/12
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