The table below lists the signal assignments for the P1 connector on the
VXI bus.
Pinouts are provided for both the slot 0 card and slots 1 to 12
[which are identical].
The VXI interface uses DIN 41612 connectors.
Manufacturers producing DIN 41612 connectors may be
found on the VME page; a link is provided below the pin out table.
Editor note; I do not believe that this specification has been updated since 1992.
| Pin # | Signal name | Signal name | Signal name |
|---|---|---|---|
| Row A | Row B | Row C | |
| 1 | D00 | BBSY* | D08 |
| 2 | D01 | BCLR* | D09 |
| 3 | D02 | ACFAIL* | D10 |
| 4 | D03 | BG0IN* | D11 |
| 5 | D04 | BG0OUT* | D12 |
| 6 | D05 | BG1IN* | D13 |
| 7 | D06 | BG1OUT* | D14 |
| 8 | D07 | BG2IN* | D15 |
| 9 | GND | BG2OUT* | GND |
| 10 | SYSCLK | BG3IN* | SYSFAIL* |
| 11 | GND | BG3OUT* | BERR* |
| 12 | DS1* | BRO* | SYSRESET* |
| 13 | DS0* | BR1* | LWORD* |
| 14 | WRITE* | BR2* | AM5 |
| 15 | GND | BR3* | A23 |
| 16 | DTACK* | AM0 | A22 |
| 17 | GND | AM1 | A21 |
| 18 | AS* | AM2 | A20 |
| 19 | GND | AM3 | A19 |
| 20 | IACK* | GND | A18 |
| 21 | IACKIN* | SERCLK | A17 |
| 22 | IACKOUT* | SERDAT* | A16 |
| 23 | AM4 | GND | A15 |
| 24 | A07 | IRQ7* | A14 |
| 25 | A06 | IRQ6* | A13 |
| 26 | A05 | IRQ5* | A12 |
| 27 | A04 | IRQ4* | A11 |
| 28 | A03 | IRQ3* | A10 |
| 29 | A02 | IRQ2* | A09 |
| 30 | A01 | IRQ1* | A08 |
| 31 | -12v | +5v Standby | +12v |
| 32 | +5v | +5v | +5v |
Both the VMEbus and VXI bus use the same P1 connector, the pin-outs and
signal names are the same.
The connector is a 96 pin DIN (41612) 3 rows x
32 pins @ IEEE 1014-1987. The pin-out for either bus is listed in the
table above. The latest VMEbus spec added two additional rows, but I'm
not sure that the up-grade has hit the VXI spec yet.
Because both bus
types can use the same P1 connector, VME cards may be used in a VXI bus.
How ever I do not believe VXI cards work in a VMEbus chassis, because of
the P2 differences.
The VMEbus signal types for P1 and P2 connectors are listed below:
Open collector signals which require Open Collector drivers and
receivers: [Working with Open Collector Pins]
ACFail, BBSY, BERR, DTACK, IACK, SERDAT, SYSFAIL, SYSRESET, [IRQ1 -
IRQ7], and [BR0 - BR3].
Three-State signals which require 3-State drivers and
receivers: [Working with 3-State Pins]
AS, DS0, DS1, DTACK, RETRY, IACK, LWORD, WRITE, [AM0 - AM5], [A01 - A31],
and [D00 - D31].
Totem-Pole signals which require Totem-Pole drivers and
receivers: [Working with Totem-Pole Pins]
BCLR, SYSCLK, SERCLK, IACKIN, IACKOUT, [BG0IN - BG3IN], [BG0OUT -
BG3OUT].
Back to the main VXI bus page for VXI bus descriptions,
or VXI P2 connector pin-outs or VXI P3 connector pinout.
The VME bus Interface description is listed on the VMEbus page.
Or use the Buses icon below to search for related interfaces.
Editor note; The signal assignment table is based on the original VXI IEEE1155-1987 standard.
The pin-out table does not account for IEEE1155-1992, or the revision to the VXI specification in 1998 or 2004.
However defined signal pins do not change between specification updates, which occur ever 5 years as the standards are reviewed.
Engineering note; like the original VME standard, the VXI standard is starting to become out-dated in regards to speed.
Site Navigation: Engineering Home > Interface Buses > Backplane Interface Standards > VXI Board Standard > VXI Board J1 Signal Assignments.
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