VHDL Code Example
Pitfalls

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VHDL coding guidelines

Latches:

As a general rule avoid using Latches in the design. Watch for inferred latches which are developed in the code and re-code to eliminate the latch. A Latch may make the design harder to verify.

VHDL Latch example [inferred Latch]:
process (enable, data_in)
begin
if enable = '1' then
q <= data_in;
end if;
end process;

Latches are inferred by "if" statements which are not be completely specified. A Latch is inferred when an "else" statement is omitted, when values are not assigned a value, or when the "event" statement is missing. To avoid a Latch being developed assign an output for all possible input conditions. Use an "else" statement instead of an "elseif" statement in the final branch of an "if" statement to avoid a latch. Be sure to assign default values at the beginning of a process to avoid an inferred latch. Two ways to avoid a Latch are provided below, the first one represents a 2-to-1 latch, and second is a normal D-type flip flop.

VHDL 2-1 Mux
process (enable, data_in)
begin
if enable = '1' then
data_out <= data_in;
else
data_out <= '0';
end if;
end process;

VHDL code for a D Flip Flop with Reset and Clear

if reset = ‘0’ then
output <= ‘0’;
elsif set = ‘0’ then
output <= ‘1’;
elsif (clock’event and clock = ‘1’) then
output <= data;
end if;
Additional examples of flip flop code is listed on the VHDL code page.

VHDL Standards:
IEEE-1076: Standard VHDL Language Reference Manual IEEE Computer Society Document
IEEE 1076.1: VHDL Analog and Mixed-Signal Extensions IEEE Computer Society Document
IEEE 1076.2: Standard VHDL Mathematical Packages IEEE Computer Society Document
IEEE 1076.3: Standard VHDL Synthesis Packages IEEE Computer Society Document
IEEE 1076.4: Standard for VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification IEEE Computer Society Document
IEEE 1076.6: Standard for VHDL Register Transfer Level (RTL) Synthesis IEEE Computer Society Document

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FPGA Manufactures: Programmable Logic ICs

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