VHDL Code Example
Pitfalls

VHDL coding guidelines

VHDL Latches:

As a general rule avoid using Latches in the design. Watch for inferred latches which are developed in the code and re-code to eliminate the latch.
A Latch may make the design harder to verify.

VHDL Latch example [inferred Latch]:
process (enable, data_in)
begin
if enable = '1' then
q <= data_in;
end if;
end process;

Reference; an 8-bit Latch IC Schematic.
Latches are inferred by "if" statements which are not be completely specified. A Latch is inferred when an "else" statement is omitted, when values are not assigned a value, or when the "event" statement is missing.
To avoid a Latch being developed assign an output for all possible input conditions. Use an "else" statement instead of an "elseif" statement in the final branch of an "if" statement to avoid a latch.
Be sure to assign default values at the beginning of a process to avoid an inferred latch. Two ways to avoid a Latch are provided below, the first one represents a 2-to-1 latch, and second is a normal D-type flip flop.

VHDL 2-1 Mux
process (enable, data_in)
begin
if enable = '1' then
data_out <= data_in;
else
data_out <= '0';
end if;
end process;

Reference; an IC Mux Schematic.
VHDL code for a D Flip Flop with Reset and Clear

if reset = ‘0’ then
output <= ‘0’;
elsif set = ‘0’ then
output <= ‘1’;
elsif (clock’event and clock = ‘1’) then
output <= data;
end if;
See VHDL code for additional examples of flip flop code.
Reference; an IC Flip Flop Schematic.
and example part numbers.

VHDL Clock Gating:

Normally the clock should never be gated. If you need to inhibit a signal you should gate the data and not the clock. The code below gates the data into a flip flop

if reset = ‘0’ then
output <= ‘0’;
elsif (clock’event and clock = ‘1’) then
if gate = ‘1’ then
output <= data;
end if;

One method to gate a clock is to combine the output from a flip flop and an AND gate or OR gate and re-register the signal.
The vhdl code below describes a FF who's output is along with a clock is feed to an AND gate which is used as the input to another FF.

if reset = ‘0’ then
output <= ‘0’;
elsif (clock’event and clock = ‘1’) then
output <= data;
end if;

if reset = ‘0’ then
out <= ‘0’
elsif (clock’event and clock = ‘0’) then
out <= ‘0’;
elsif (output = ‘0’ and clock = ‘1’) then
out <= ‘0’;
elsif (output = ‘1’ and clock = ‘0’) then
out <= ‘0’;
elsif (output = ‘1’ and clock = ‘1’) then
output <= ‘1’;
end if;

Related topics:
VHDL Info Sites: Listed here, examples of VHDL code.
Back to the Logic Design Page, Digital Logic Pitfalls
VHDL Design Tools: CAD - CAE Products
VHDL Simulation Tools: VHDL Simulation Software Vendors
FPGA Manufactures: Programmable Logic ICs

VHDL Standards:
IEEE-1076: Standard VHDL Language Reference Manual IEEE Computer Society Document
IEEE 1076.1: VHDL Analog and Mixed-Signal Extensions IEEE Computer Society Document
IEEE 1076.2: Standard VHDL Mathematical Packages IEEE Computer Society Document
IEEE 1076.3: Standard VHDL Synthesis Packages IEEE Computer Society Document
IEEE 1076.4: Standard for VITAL ASIC (Application Specific Integrated Circuit) Modeling Specification IEEE Computer Society Document
IEEE 1076.6: Standard for VHDL Register Transfer Level (RTL) Synthesis IEEE Computer Society Document

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