Trace Termination

[Series Termination] [Parallel Termination] [Thevenin Termination]
[AC Termination] [Differential Termination] [Termination Examples]
[PWB Materials] [Signal Reflection Calculation]
[Logic Design Page]

A few more design rules and observations:

1.   Multiple reflections at one node algebraically add together;
so three incoming reflections shown above will algebraically add together, I leave it to the reader.

2.   Three major conditions:
    Matched Load: RL = Zo:     Vr / Vi = 0, No reflection.
    Open Load:      RL = ∞        Vr / Vi = +1 Full reflection, with same polarity.
    Shorted Load:   RL = 0:       Vr / Vi = -1 Full reflection, with inverted polarity.

Multiple reflections adding at a node

3.   An unterminated line to an IC will normally have a 1Meg ohm input resistance and a 10pF input capacitance for an impedance of (R2 + XC 2) 1/2 = 1Meg Ohm.
Most Integrated Circuits will be CMOS devices with FET input circuits.

4.   A PWB trace has a very small resistance and offers no real attenuation to the reflection. The impedance [Zo] of a PCB trace;
     Zo = ([R + XL] / XC)1/2

5.   A signal is attenuated as it propagates down the net by: e-TL * [(RW + jXL) * (XC) )]1/2
     RW = 2 * 3.1415 * Freq. * R = Skin effect on trace resistance.
     XL = 2 * 3.1415 * Freq. * L = Inductor impedance at some frequency.
     XC = 2 * 3.1415 * Freq. * C = Capacitor impedance at some frequency.
     TL = Trace length

6.   If a load is terminated correctly "matched" [using one of the options listed at the top of the page] no reflection will occur. If the load is unterminated a reflection will occur. If the net goes into a CLK of a flip flop the device may be double clocked, as shown above. Not having a termination is what causes ringing on Transmission lines.

7.   The Initial voltage amplitude on the line is equal to: Vs * [Zo / (Zs + Zo)], the final voltage on the line is equal to: Vs * [Zi / (Zs + Zi)]. The final voltage occurs after the transmission line effects have dissipated. In both cases, it's just a simple voltage divider.

8.   Small changes in either the source resistance [impedance] or trace impedance have a major impact on the reflections [oscillations] on the net. Changing the source resistance 7 ohms, [20 ohms to 13 ohms shown above] caused the circuit to malfunction. The circuit designer has no control over the internal source resistance of a device, and little control over the trace impedance. Assume a 20% deviation in trace impedance from what was specified, and at least a 20% change in source resistance. However, I would not bet the design on characteristics which I could not control ~ the save bet is add the termination if required.

9.   Some circuit designs require the reflection to build up the voltage on the line. Circuit designs which require the reflection are termed reflected wave switching. These designs have accounted for the issues discussed on this page.

10.   Discontinuities in the trace impedance cause reflections. A discontinuity may be caused by a trace corner, bend, a necked trace [to fit between pins] an IC pin, or trace vias. Discontinuities are not covered on this page; however, the trace mismatch is small but still produces a reflection. The reflection results are much more complex as the number of discontinuities grow.

11.   The oscillations [ringing] rise / fall time is based on the circuit [trace] or cable characteristics.

12.   As stated above, some of the resistor termination networks don't always terminate the line to the exact value of the trace. It is possible to get the values close to reduce the amount of the reflection, and still use a different resistor value. A designer may do this to use a resistor value already called out in the parts list, or because the value would be so low the driver IC may not correctly drive the load.

13.   Simulation of the circuit will account for any issue listed here. The circuit should be simulated for any trace length which exceeds Length > tr / [ 6 x t pr ]. The trace must be terminated for any trace length which exceeds Length > tr / [ 2 x t pr ]. The length will change as the logic family used changes, because the rise time [tr] changes for each logic family. The Signal propagation rate [t pr] depends on the board material, and is not well controlled. The propagation rate will differ for surface traces [Microstrip] or embedded traces [Stripline].

14.   Trace impedance is inversely proportional to trace width and directly proportional to trace height above the ground plane. Here are a few examples:
Microstrip at 50 ohms; Every 0.5mil change in trace width changes the impedance by 2 ohms. For a 1mil change in distance from the ground plane is an impedance change of 8 ohms. Doubling the trace thickness results in an impedance change of 8 ohms.
Stripline at 50 ohms; Every 0.5mil change in trace width changes the impedance by 2 ohms. For a 4mil change in distance from the ground plane is an impedance change of 5 ohms. Doubling the trace thickness results in an impedance change of 5 ohms.

15.   The page uses PWB circuit trace characteristics and equations, but the same is true for any cable; coax cable, ribbon cable, twisted ribbon pair cable, or cable pair.

Related pages on this site:
PWB Info PWB Terms Component Chip Sizes Capacitor IC By-Pass Info Resistor Pull-Up equations

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Modified 3/05/12
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