[**Series Termination**]
[**Parallel Termination**]
[**Thevenin Termination**]

[**AC Termination**]
[**Differential Termination**]
[**Termination Examples**]

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So; How do you know when to terminate a PCB trace or cable? Regardless of the clock or data frequency the design uses, the Effective Operating Frequency of a circuit, or trace is: Signal Frequency [GHz] = [0.35] / [Signal Transition Time {nSec}]. For signal Transition time, use the shorter value of T_{r} [Rise Time] or T_{f} [Fall Time]. For example: a design that uses a signal period of 50MHz with a 1.1nS rise time [or fall time] has an Effective Operating Frequency of 318MHz ~ which is far above the actual operating frequency [Period] of the signal. The **Freq _{Knee}** = 0.5/T

PWB traces [or cables] should be terminated (using one of the schemes listed below) when the trace length exceeds the following:

Where

For a general approximation this page uses: 150ps/inch for FR4 [Board Material], and 130pS/inch for Polimide [Board Material]. For example, using FR4 [150ps/inch] a trace with a 1.1nS rise time would need to be terminated if it exceeded 3.3 inches. The four main ways to terminate a signal trace are shown below. Calculations for Signal propagation rate [by board type], and reflection amplitude and frequency are shown after the termination examples.

As a side note: A Printed Wiring Board [PWB] trace really has no resistance [because it's very low], this page deals with Printed Wiring Board trace impedance. The resistance of a Printed Wiring Board trace has more to do with voltage drop over the signal line [trace] and nothing to do with signal reflections ~ which this page deals with. This page uses the terms Printed Wiring Board, or PWB, and Printed Circuit Card, or PCC, and Circuit Card Assembly, CCA Interchangeably. Unused IC input pins which require a Resistor pull-up are not discussed on this page.

Also the information provided works for terminating a cable in addition to a board trace.

Series Termination |
V_{C} = 1 - e^{-(t/RC)} |

**Parallel Termination** dissipates the most power (at low clock rates), but only requires one resistor. Parallel Termination will work with any number of loads. The termination resistor [R] is still selected to match the trace impedance [Z_{o}] and may be taken to GND or Vcc [the Power Supply]. The large power dissipation occurs at low switching rates, while at faster clock rates the driver is switching all the time any how. V_{OH} = the Voltage Output when High [watch the amount of current you can source], and V_{OL} = Voltage Output when Low [watch the amount of current you can sink]. A reflection will occur when the termination resistor [R] does not match the trace impedance [Z_{o}], some people set the termination resistor a bit higher then Z_{o} to reduce the amplitude of the reflection [because the trace impedance is to low to match].

**Thevenin Termination** [or Split Termination] allows the selection of the correct voltage and impedance of the line, but don't use with floating outputs. This Termination scheme also provides a constant DC path, but the resistor values are normally twice as large as with Parallel Termination. The two resistors [R_{1} and R_{2}] (in parallel) should be chosen to equal the line impedance [Z_{o}], and the Thevenin voltage should be chosen to provide V_{T} for the logic family being used. So the constant current demand calculation is V_{cc} / [R_{1} + R_{2}], and the demand from the driving device is V_{o} / R_{1}. ECL devices will pull the lower resistor to V_{ee}, and not ground. Use the equations below to solve for the ECL values:

**R _{1}** = Z

A capacitor may also be used to eliminate steady state DC current flow. See **AC Trace Termination** below.

The SCSI Bus uses **R _{1}** = 330 ohms, and

The VME Bus uses

The GPIB Bus uses

In some cases resistor packages are used to supply a number of terminations;

MIL-PRF-83401/9 defines 8 Thevenin Terminations in a SIP package.

Refer to this Resistor dictionary page for a definition of Thevenin.

Also refer to Resistor Network Manufacturers, or Resistor Array Schematics and common values.

AC Termination |
_{r}] / Z_{o}. The capacitor value may be traded off to select a lower value [below 200pF] for low power consumption, or higher values for a cleaner waveform but a higher power consumption at higher frequencies.X = 1 / [ 2 * 3.1415 * F * C] = Capacitive Reactance _{c}F = Frequency of the signal, and C = the value of the CapacitorT = Rise Time of the signal [in nS], and _{r}Z = Trace Impedance.
_{o} |

Differential lines also require a termination resistor if the line length exceeds the data rate, from the equation at the top of the page. The termination is placed at the destination. To reduce the current consumption AC termination may be used [but not very common]. AC Termination of a line results in the lowest power drain, but also requires two parts. Current only flows while the capacitor is charging. The termination resistor [R] is still selected to match the trace impedance [Z_{o}], while the capacitor is selected by: **X _{c}** = [3 * T

Half-Duplex Circuits, which transmit in both directions need to be terminated at both ends of the trace. So that the destination at each end has a termination resistor.

Only two termination resistors are to be used. If there are other loads [transceiver] on the bus they should be left un-terminated.

Another example for Differential Trace Termination includes SCSI **Terminations** which reside on both sides of the bus.

The center picture provides a Differential Trace Resistor Termination for the SCSI bus.

Passive Termination provided reliable operation in SCSI-1 systems, how ever for systems using SCSI-2 and above require active termination schemes. The primary problem is double clocking on the Strobe lines, which may occur because of a reflection. Of course the passive approach also has a constant resistive path from TERMPWR to ground. The Active approach provides a stable voltage to the terminating resistor. Another technique involves FPT [Forced Perfect Termination] which uses the high switching speed of Hot-Carrier Schottky diodes to approximate the perfect termination.

The termination resistor should always be placed as close to the final destination as possible, of course Series termination, or source termination should be placed near the source. Placing the termination at the far end just at the input pin works well in many situations. For larger chips, such as FPGA's, which can be 1 inch square a technique called Fly-By termination is used. Fly-By termination places the termination past the device which puts the termination at the end of the trace. In this case Fly-By termination increases the trace length by an inch, the resistor is still an inch from the input pin, but at the end of the trace and not an inch before the input pin.

The bus should not be Y-ed [Left drawing] if the speed of the circuit and length of the trace act as a transmission line. The bus may be Y-ed if the trace does not appear as a transmission line based on the equation listed above. Normally the trace should be daisy-chained from device to device [center drawing]. Some high speed circuits like memory chips require the signal to reach all devices on the chain at the same time [right drawing]. If the circuit is Distributed, where T_{r} is less then 4 times T_{pd} you don't need to worry about the routing. How ever if the circuit is lumped then it needs to be viewed as a transmission line. A lumped circuit occurs when T_{r} is greater then 4 times T_{pd}. **T _{r}** = Rise Time of the signal,

The reflection coefficient used below is based on the following equations, the numbers provided are used in the example to follow.

The Source Reflection [going from the source to the destination] = P_{S}

**P _{S}** = [Z

The Load Reflection [going from the destination to the source] = P

The maximum value for the reflection coefficient is +/-1. If the device impedance is larger then the trace impedance, the reflection coefficient is positive. If the impedance is smaller then the trace impedance, the reflection coefficient is negative.

The starting voltage from the source is based on the voltage division between Z

V

It's 2.9 volts [V

The above figure shows a typical circuit, with one driver and one receiver. The driver has a [internal] source resistance of 20 ohms, the trace impedance is 70 ohms and the input resistance on the receiver is 20k ohms. The line has not been terminated, the 20k is the internal impedance of the device.

The lattice diagram gives the voltage for both source and destination after each reflection. The waveforms are shown to the right, Green for Source, Blue for Destination. The difference in [switching] time is based on the trip delay. The source or destination will switch one trip delay from one another [1.05nS in this example]. The times provided are dependent on the trace length. The important points are 'A' and 'B'. Point 'A' is an over voltage **[Overshoot]** at the destination, which is given as maximum V_{IN} in the data sheet. Point 'B' is an under voltage **[Undershoot]**, or loss of noise margin. Noise Margin V_{NH} is the difference between V_{OH} min - V_{IH} min, or 2.9v - 2.0v = 0.9v = V_{NH}. In this case the destination sees 2.2v instead of 2.9v which is a normal minimum V_{OH}, so V_{NH} = 2.2v - 2.0v = 0.2 volt noise margin.

Another common source impedance is 13 ohms [instead of the 20 ohms listed], which produces an even greater magnitude in reflections. Again, the maximum value for the reflection coefficient is +/-1. The voltage at either the source or destination in the graphic above is based on the sum of the; current voltage + incoming reflection voltage + outgoing reflection voltage.

If this is a data line than the loss of noise margin is a don't care, unless the clock gates the circuit at this time. It gets harder with a 32 bit bus, with each line [reflection] shifting by 150pS [per inch] for each trace length ~ so you have to check them all. The problem compounds if the trace is a clock line ~ a double rising edge pulse on the clock line.

Reducing the Source resistor [Z_{S}] to a more realistic value of 13 ohms, and leaving the destination unterminated produces the following change:

V_{OH} [min] * [Z_{O} / [Z_{S} + Z_{O}]] changes to 2.44 volts [instead of 2.2v].

The Source reflection coefficient is now 0.69 [instead of 0.5].

The larger initial voltage and higher reflection coefficient will produce more severe reflections [ringing].

So this low output impedance is more in line with what you might find. Most devices have a high input impedance and a low output impedance. With the new low level [1.77v] at the receiving device [blue line], the noise margin is gone. The incoming 1.77 volt signal is both an invalid voltage level and with the next rising edge ~ the second clock transition [if the signal is a clock].

In addition PWB trace impedances are hard to control, so it will vary from what may have been specified. Also, the output impedance of the driver [Z_{S}] may be dynamic and may change with current demand or vary from device to device. Finally, the input impedance of the receiver [Z_{i}] will normally be much greater then the 20k shown. Most devices will have FET inputs, so Z_{i} will be infinite resulting in a reflection coefficient of 1 instead of the 0.99 used. To make matters worse there may be other reflections occurring on the traces above which are not shown. Reflections due to trace via's, moving from one PWB layer to another, or other devices on the line may reduce the 1.77v low level shown above even more.

Another more complex example would be to allow the trace impedance to change, because it passed to another layer in the PWB. Keeping the same Input and output IC impedance while changing the trace impedance results in the lattice diagram below. The interesting point here [other then the more complex voltage calculations] is that the first trace may have one length while the second trace segment has another. So reflection 'd' may not intersect with reflection 'e' ~ they occur at different times. The example for different trace segments is shown as the smaller lattice diagram to the far right [below]. The resulting reflection will no longer appear has a damped Sine wave, and will look more complex. The reflection wave-forms shown in the first two examples above are damped SIN waves {signals don't really have 0 rise times], they are just drawn as square waves because that's how it's normally shown...

The circuit shown above shows a PWB trace running on one layer of the board as a 50 ohm trace and then running on another layer as a 70 ohm trace. Keep in mind that as the trace transitioned from one layer to another it passed through a via, which is normally considered to be a low pass filter. A via is also an uncontrolled [unknown] impedance. So the graphic above should also show another [Z_{o}] to represent the via. The equations are presented below:

**V _{i}** = V

A = a, | A' = b + e |

B = a + c + d, | B' = b + e + g + i |

C = A + c + d + f + h, | C' = b + e + g + i + k + l |

T = 1 + _{2}P_{2} | T = 1 + _{3}P_{3} |

**a** = V_{i},
**b** = a * T_{2},
**c** = a * *P*_{2},
**d** = c * *P*_{1}

**e** = b * *P*_{4},
**f** = d * *P*_{2} + e * T_{3},
**g** = e * *P*_{3} + d * T_{2},

**h** = f * *P*_{1},
**i** = g * *P*_{4},
**j** = h * *P*_{2} + i * T_{3},
**k** = i * *P*_{3} + h * T_{3},
**l** = k * *P*_{4}

So solving the equations above gives these results:

**A** = 2.3 volts = a = V_{i}, the starting step voltage on the net.

**A'** = 5.34 volts, which represents the __over-voltage__*Overshoot* at the destination.

**B** = 2.46 volts, seen at the source.

**B'** = 3.9 volts, seen at the destination.

**C** = 3.36 volts, seen at the source.

**C'** = 1.06 volts, which represents the __under-voltage__*Undershoot* at the destination.

So now we have an over voltage which reaches above 5 volts on a 3.3 volt circuit. We also have a voltage at the destination IC which moves from 5.34 and then down to a low of 1.06 volts. The 1.06v level is well below the 1.85v Threshold Voltage for a 3.3v CMOS integrated circuit. Assuming this is a clock line into a Flip Flop, it produces a double clock [before the data had a chance to change]. We can also assume that this circuit will not function correctly, and by point C' the ringing has not even damped out yet. The reflections are still occurring after point C', they are just not shown above. The reflections will damp out as an exponential decay, and will continue based on this calculation:

*t* = (Trace_{Length} * (LC)^{1/2}) / -In[P_{S}(2*3.14*F_{knee})P_{i}*2*2.14*F_{knee})]

As a side note, you could also solve for the standing voltage between the two trace impedances ~ if there were a third IC on the net.

**A few more design rules:**

The material the printed wiring board is fabricated with determines its dielectric constant. The dielectric constant in turn determines the time in which signals propagate over the board **[Propagation velocity]**. This discussion now listed on the **PWB Materials**

Design Rules have moved to a new page; Trace Termination Rules

PWB Info | Ground/Power Planes | Component Chip Sizes | Capacitor IC By-Pass Info | Resistor Pull-Up equations |

The signal destination is either called the Trace Load, Termination Load or Receiver Load depending on the device at the end of the line [with the trace load being the Unterminated condition on the Net].

Use a Matched Load to prevent Overshoot and Undershoot [also called ringing] which are both conditions caused by mis-termination.

Depending on the Integrated Circuit type or the Glue Logic Family used [i.e. CMOS, TTL] the trace termination may also have to change.

**{Printed Wiring Board Trace Termination top}**

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