PXI Connector P2 Pin Out and Signal names

The PXI connector P2 [J2] System slot pinout is provided below. There is only one System slot defined in a PXI backplane.
The PXI P2 connector pinout for the Peripheral slot is provided on its own page.
The pinout is also the same as the CompactPCI pinout. cPCI is electrically identical to the PCI specification, it uses the same signals.
However some signals have been added in addition to the PCI specification.
Refer to the PXI P1 pinout page for P1/J1 Pin outs [32-bit PCI signals].
For clarity the PXI signal name labels on signal rows Z and F have been combined, while still being defined as separate pins.

**PXI P2 Connector Pin Out; System Slot**
Pin	Signal name	Signal name	Signal name	Signal name	Signal name	Signal name	Signal name
--	Row Z	Row A	Row B	Row C	Row D	Row E	Row F
22	GND Ground	PXI_RSVA22	PXI_RSVB22	PXI_RSVC22	PXI_RSVD22	PXI_RSVE22	GND Ground
21		CLK6	GND	RSV	RSV	RSV
20		CLK5	GND	RSV	GND	RSV
19		GND	GND	RSV	RSV	RSV
18		PXI_TRIG3	PXI_TRIG4	PXI_TRIG5	GND	PXI_TRIG6
17		PXI_TRIG2	GND	PRST#	REQ6#	GNT6#
16		PXI_TRIG1	PXI_TRIG0	DEG#	GND	PXI_TRIG7
15		PXI_BRSVA15	GND	FAL#	REQ5#	GNT5#
14		AD[35]	AD[34]	AD[33]	GND	AD[32]
13		AD[38]	GND	V(I/O)	AD[37]	AD[36]
12		AD[42]	AD[41]	AD[40]	GND	AD[39]
11		AD[45]	GND	V(I/O)	AD[44]	AD[43]
10		AD[49]	AD[48]	AD[47]	GND	AD[46]
9		AD[52]	GND	V(I/O)	AD[51]	AD[50]
8		AD[56]	AD[55]	AD[54]	GND	AD[53]
7		AD[59]	GND	V(I/O)	AD[58]	AD[57]
6		AD[63]	AD[62]	AD[61]	GND	AD[60]
5		C/BE[5]#	GND	V(I/O)	C/BE[4]#	PAR64
4		V(I/O)	PXI_BRSVB4	C/BE[7]#	GND	C/BE[6]#
3		CLK4	GND	GNT3#	REQ4#	GNT4#
2		CLK2	CLK3	SYSEN#	GNT2#	REQ3#
1		CLK1	GND	REQ1#	GNT1#	REQ2#

The PXI System slot pin out for P2/J2 is provided above. cPCI is electrically identical to the PCI specification, it uses the same signals. However some have been added in addition to the PCI specification. Additional notes:
The number sign in the pinout table above refers to: "A # symbol at the end of a signal name indicates that the signals asserted state occurs when it is at a low voltage. The absence of a # symbol indicates that the signal is asserted at a high voltage.
The V(I/O) pins are un-named in this table. In a +5 volt system the V(I/O) pins are +5volts, in a +3.3volt system the V(I/O) pins are +3.3 volts.

cPCI uses 2mm 'Hard Metric'; IEC 1076-4-101, a number of different pin arrangements. Normally the outside Ground rows (which are compression pins) 'Z' and 'F' are not counted as pins. OEM pin numbering may be by cPCI or in accordance with IEC 61076-4-101 (which is reversed). The term "Hard Metric" only means that metric dimensions are preferred ~ with-out regard to inches.

cPCI 2mm connectors mating distances [12.50mm] matches the 96 pin DIN 41612 connectors used with other EuroCard packaging [IEC 273 or IEEE 1101, 1101.10], like VMEbus. FutureBus connectors, which also use 2mm style has a mating distance of 10mm, and is not compatible with cPCI connectors.

The connector styles below are counting signal pins (not the ground rows), as indicated on many data sheets:

Type A connector; 110 pins, Keyed (J1/J4),([25 rows x 5 columns] - [3 rows x 5 columns of Key])
Type B connector; 110 pins (J2/J5), [22 x 5]
Type B connector; 95 pins (J3), [19 x 5]. This is also used as P0 with VME64
Type C connector; 55 pins [11 x 5]
Type AB; 95, 110, or 125 pins

There are other types:
Type L connector; # contact cavities to accept power insert contacts
Type M connector; # contact cavities to accept power insert contacts/with half the connector having normal pins

Site Navigation: Engineering Home > Electrical Buses > Backplane Buses > PXI Bus > P2 I/O.

Back to the main PXI Compact PCI [cPCI] for Instrumentation Bus page, which contain a description of the bus, connector manufacturer, and IC manufacturer links.


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