The EISA (Extended Industry Standard Architecture) or Enhanced ISA bus
operated at 8MHz using a 8/16/32 bit data bus. The EISA interface was
another PC Expansion Bus which was also compatible with ISA. An ISA card
will work in a EISA slot, but an EISA board will not work in an AT slot.
All of the PC-XT and PC-AT fingers reside on an EISA board/connector. The
actual EISA fingers (pin) reside below the XT and AT fingers on an EISA
board. The EISA bus (in one mode) used both edges of the clock, with the
rising edge used to output address, and the falling edge to place the
data on the bus. Three other transfer modes were available. The EISA bus
does not allow the board skirts that were common with the older XT cards.
The EISA cards are the same size as the AT cards [shown below].
The new address lines
are called "LA#", and all address lines are latched. Refer to the EISA Pinout
table below for EISA signal names and pin out information.
The Board size and Pinout for the Extended Industry Standard Architecture
[EISA] bus is shown below. The EISA bus may also be called the Enhanced
ISA bus.
The EISA bus is obsolete and should not be used for new systems.
However the pin out table may be used for legacy computer systems.
Pin | ||||||||
# | ||||||||
1 | Channel Check | Ground | CMD | GND | System Enable | Memory 16 bit select | LA7 | LA8 |
2 | Data 7 | Reset | START | +5 volt | Unlatched Address 22 | I/O 16bit Chip Select | GND | LA6 |
3 | Data 6 | +5v | EXRDY | +5 volt | Unlatched Address 23 | IRQ10 | LA4 | LA5 |
4 | Data 5 | IRQ9 | EX32 | Reserved | Unlatched Address 21 | IRQ11 | LA3 | +5 volt |
5 | Data 4 | -5v | GND | Reserved | Unlatched Address 20 | IRQ12 | GND | LA2 |
6 | Data 3 | DMA Request 2 | KEY | KEY | Unlatched Address 19 | IRQ15 | KEY | KEY |
7 | Data 2 | -12v | EX16 | Reserved | Unlatched Address 18 | IRQ14 | SD17 | SD16 |
8 | Data 1 | Zero Wait State | SLBURST | Reserved | Unlatched Address 17 | DMA ACK0 | SD19 | SD18 |
9 | Data 0 | +12v | MSBURST | +12 volt | Memory Read | DMA Request 0 | SD20 | GND |
10 | I/O Channel Ready | Ground | W/R | M/IO | Memory Write | DMA ACK5 | SD22 | SD21 |
11 | Address Enable | Real Memory Write | GND | LOCK | Data 8 | DMA Request 5 | GND | SD23 |
12 | Address 19 | Real Memory Read | RESERVED | RESERVED | Data 9 | DMA ACK6 | SD25 | SD24 |
13 | Address 18 | I/O Write | RESERVED | GND | Data 10 | DMA Request 6 | SD26 | GND |
14 | Address 17 | I/O Read | RESERVED | RESERVED | Data 11 | DMA ACK7 | SD28 | SD27 |
15 | Address 16 | DMA ACK3 | GND | BE3 | Data 12 | DMA request 7 | KEY | KEY |
16 | Address 15 | DMA Request 3 | KEY | KEY | Data 13 | +5v | GND | SD29 |
17 | Address 14 | DMA ACK1 | BE1 | BE2 | Data 14 | Master | SD30 | +5 volts |
18 | Address 13 | DMA Request 1 | LA31 | BEQ | Data 15 | Ground | SD31 | +5 volts |
19 | Address 12 | Refresh | GND | GND | N/A | N/A | MREQ | MAK |
20 | Address 11 | CLK | LA30 | +5 volts | N/A | N/A | ||
21 | Address 10 | IRQ7 | LA28 | BEQ | ||||
22 | Address 9 | IRQ6 | LA27 | GND | ||||
23 | Address 8 | IRQ5 | LA25 | LA26 | ||||
24 | Address 7 | IRQ4 | GND | LA24 | ||||
25 | Address 6 | IRQ3 | KEY | KEY | ||||
26 | Address 5 | DMA ACK2 | LA15 | LA16 | ||||
27 | Address 4 | Terminal Count | LA13 | LA14 | ||||
28 | Address 3 | Address Latch En | LA12 | +5 volt | ||||
29 | Address 2 | +5v | LA11 | +5 volt | ||||
30 | Address 1 | Oscillator | GND | GND | ||||
31 | Address 0 | Ground | LA9 | LA10 |
The PCXT bus pinout uses the J1 A/B rows, and a PCAT
bus pinout uses the J1 [A/B rows] and J2 [C/D rows] connectors. The
PC EISA pinout uses all rows of both J1 and J2. The EISA bus
added rows 'E', 'F', 'G', and 'H' under the XT and AT pins. The
fingers are copper strips on the PWB spaced on 0.1 inch centers. |
Of course this page was originally written when it was possible to find a EISA card in service.
These days the obsolete EISA interface is no longer used and is out-of-date.
Any EISA card would have been replaced by some other board long ago, even with the long cycles of military designs or products.
As with a number of legacy interfaces, the information is offered as is, but no attempt should be made to use the data.
This data is obsolete and should not be used in any new design. Well the approach and speeds are obsolete.
Notice that most of the integrated circuits used in the photo of the EISA card are low density LSI glue logic ICs.
Current designs might use a few surface mount SOICs, but much of the circuitry could be contained within a single FPGA.
Return to the main PC AT bus page [ISA Expansion Bus].
Topic Navigation: Engineering Home > Interface Buses > Personal Computer Buses > PC AT Expansion Bus > EISA Expansion Card.
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