PCI Bus pinout for both 32 bit and 64 bit cards is shown
below;
Signal Pins 63-94 are only used on 64 bit PCI bus cards. The PCI pinout
for the 32 bit bus stops at the key-way [Spacer], while the 64 bit pinout
occupies the entire table. The PCI local bus was used in personal
computers to provide expansion slots for add-on cards to the motherboard. The PCI bus replaced the
ISA PC-AT expansion slot in PCs.
The PCI local bus is not the same as
the new PCI Express bus which has a completly
different pinout.
The number sign in the pinout table below refers to: "A # symbol at the end of a signal name indicates that the signal’s asserted state occurs when it is at a low voltage. The absence of a # symbol indicates that the signal is asserted at a high voltage.
| Pin # | Name | PCI Pin Description | Pin # | Name | PCI Pin Description |
|---|---|---|---|---|---|
| A1 | TRST | Test Logic Reset | B1 | -12V | -12 VDC |
| A2 | +12V | +12 VDC | B2 | TCK | Test Clock |
| A3 | TMS | Test Mde Select | B3 | GND | Ground |
| A4 | TDI | Test Data Input | B4 | TDO | Test Data Output |
| A5 | +5V | +5 VDC | B5 | +5V | +5 VDC |
| A6 | INTA | Interrupt A | B6 | +5V | +5 VDC |
| A7 | INTC | Interrupt C | B7 | INTB | Interrupt B |
| A8 | +5V | +5 VDC | B8 | INTD | Interrupt D |
| A9 | ----- | Reserved | B9 | PRSNT1 | Present |
| A10 | +5V | Power (+5 V or +3.3 V) | B10 | ----- | Reserved |
| A11 | ----- | Reserved | B11 | PRSNT2 | Present |
| A12 | GND03 | Ground or Keyway for 3.3/Universal PWB | B12 | GND | Ground or Keyway for 3.3/Universal PWB |
| A13 | GND05 | Ground or Keyway for 3.3/Universal PWB | B13 | GND | Ground or Open (Key) for 3.3/Universal PWB |
| A14 | 3.3Vaux | ----- | B14 | RES | Reserved |
| A15 | RESET | Reset | B15 | GND | Ground |
| A16 | +5V | Power (+5 V or +3.3 V) | B16 | CLK | Clock |
| A17 | GNT | Grant PCI use | B17 | GND | Ground |
| A18 | GND08 | Ground | B18 | REQ | Request |
| A19 | PME# | Power Management Event | B19 | +5V | Power (+5 V or +3.3 V) |
| A20 | AD30 | Address/Data 30 | B20 | AD31 | Address/Data 31 |
| A21 | +3.3V01 | +3.3 VDC | B21 | AD29 | Address/Data 29 |
| A22 | AD28 | Address/Data 28 | B22 | GND | Ground |
| A23 | AD26 | Address/Data 26 | B23 | AD27 | Address/Data 27 |
| A24 | GND10 | Ground | B24 | AD25 | Address/Data 25 |
| A25 | AD24 | Address/Data 24 | B25 | +3.3V | +3.3VDC |
| A26 | IDSEL | Initialization Device Select | B26 | C/BE3 | Command, Byte Enable 3 |
| A27 | +3.3V03 | +3.3 VDC | B27 | AD23 | Address/Data 23 |
| A28 | AD22 | Address/Data 22 | B28 | GND | Ground |
| A29 | AD20 | Address/Data 20 | B29 | AD21 | Address/Data 21 |
| A30 | GND12 | Ground | B30 | AD19 | Address/Data 19 |
| A31 | AD18 | Address/Data 18 | B31 | +3.3V | +3.3 VDC |
| A32 | AD16 | Address/Data 16 | B32 | AD17 | Address/Data 17 |
| A33 | +3.3V05 | +3.3 VDC | B33 | C/BE2 | Command, Byte Enable 2 |
| A34 | FRAME | Address or Data phase | B34 | GND13 | Ground |
| A35 | GND14 | Ground | B35 | IRDY# | Initiator Ready |
| A36 | TRDY# | Target Ready | B36 | +3.3V06 | +3.3 VDC |
| A37 | GND15 | Ground | B37 | DEVSEL | Device Select |
| A38 | STOP | Stop Transfer Cycle | B38 | GND16 | Ground |
| A39 | +3.3V07 | +3.3 VDC | B39 | LOCK# | Lock bus |
| A40 | ----- | Reserved | B40 | PERR# | Parity Error |
| A41 | ----- | Reserved | B41 | +3.3V08 | +3.3 VDC |
| A42 | GND17 | Ground | B42 | SERR# | System Error |
| A43 | PAR | Parity | B43 | +3.3V09 | +3.3 VDC |
| A44 | AD15 | Address/Data 15 | B44 | C/BE1 | Command, Byte Enable 1 |
| A45 | +3.3V10 | +3.3 VDC | B45 | AD14 | Address/Data 14 |
| A46 | AD13 | Address/Data 13 | B46 | GND18 | Ground |
| A47 | AD11 | Address/Data 11 | B47 | AD12 | Address/Data 12 |
| A48 | GND19 | Ground | B48 | AD10 | Address/Data 10 |
| A49 | AD9 | Address/Data 9 | B49 | GND20 | Ground |
| A50 | Keyway | Open or Ground for 3.3V PWB | B50 | Keyway | Open or Ground for 3.3V PWB |
| A51 | Keyway | Open or Ground for 3.3V PWB | B51 | Keyway | Open or Ground for 3.3V PWB |
| A52 | C/BE0 | Command, Byte Enable 0 | B52 | AD8 | Address/Data 8 |
| A53 | +3.3V11 | +3.3 VDC | B53 | AD7 | Address/Data 7 |
| A54 | AD6 | Address/Data 6 | B54 | +3.3V12 | +3.3 VDC |
| A55 | AD4 | Address/Data 4 | B55 | AD5 | Address/Data 5 |
| A56 | GND21 | Ground | B56 | AD3 | Address/Data 3 |
| A57 | AD2 | Address/Data 2 | B57 | GND22 | Ground |
| A58 | AD0 | Address/Data 0 | B58 | AD1 | Address/Data 1 |
| A59 | +5V | Power (+5 V or +3.3 V) | B59 | VCC08 | Power (+5 V or +3.3 V) |
| A60 | REQ64 | Request 64 bit | B60 | ACK64 | Acknowledge 64 bit |
| A61 | VCC11 | +5 VDC | B61 | VCC10 | +5 VDC |
| A62 | VCC13 | +5 VDC | B62 | VCC12 | +5 VDC |
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| A63 | GND | Ground | B63 | RES | Reserved |
| A64 | C/BE[7]# | Command, Byte Enable 7 | B64 | GND | Ground |
| A65 | C/BE[5]# | Command, Byte Enable 5 | B65 | C/BE[6]# | Command, Byte Enable 6 |
| A66 | +5V | Power (+5 V or +3.3 V) | B66 | C/BE[4]# | Command, Byte Enable 4 |
| A67 | PAR64 | Parity 64 | B67 | GND | Ground |
| A68 | AD62 | Address/Data 62 | B68 | AD63 | Address/Data 63 |
| A69 | GND | Ground | B69 | AD61 | Address/Data 61 |
| A70 | AD60 | Address/Data 60 | B70 | +5V | Power (+5 V or +3.3 V) |
| A71 | AD58 | Address/Data 58 | B71 | AD59 | Address/Data 59 |
| A72 | GND | Ground | B72 | AD57 | Address/Data 57 |
| A73 | AD56 | Address/Data 56 | B73 | GND | Ground |
| A74 | AD54 | Address/Data 54 | B74 | AD55 | Address/Data 55 |
| A75 | +5V | Power (+5 V or +3.3 V) | B75 | AD53 | Address/Data 53 |
| A76 | AD52 | Address/Data 52 | B76 | GND | Ground |
| A77 | AD50 | Address/Data 50 | B77 | AD51 | Address/Data 51 |
| A78 | GND | Ground | B78 | AD49 | Address/Data 49 |
| A79 | AD48 | Address/Data 48 | B79 | +5V | Power (+5 V or +3.3 V) |
| A80 | AD46 | Address/Data 46 | B80 | AD47 | Address/Data 47 |
| A81 | GND | Ground | B81 | AD45 | Address/Data 45 |
| A82 | AD44 | Address/Data 44 | B82 | GND | Ground |
| A83 | AD42 | Address/Data 42 | B83 | AD43 | Address/Data 43 |
| A84 | +5V | Power (+5 V or +3.3 V) | B84 | AD41 | Address/Data 41 |
| A85 | AD40 | Address/Data 40 | B85 | GND | Ground |
| A86 | AD38 | Address/Data 38 | B86 | AD39 | Address/Data 39 |
| A87 | GND | Ground | B87 | AD37 | Address/Data 37 |
| A88 | AD36 | Address/Data 36 | B88 | +5V | Power (+5 V or +3.3 V) |
| A89 | AD34 | Address/Data 34 | B89 | AD35 | Address/Data 35 |
| A90 | GND | Ground | B90 | AD33 | Address/Data 33 |
| A91 | AD32 | Address/Data 32 | B91 | GND | Ground |
| A92 | RES | Reserved | B92 | RES | Reserved |
| A93 | GND | Ground | B93 | RES | Reserved |
| A94 | RES | Reserved | B94 | GND | Ground |
| Address/Data Bus: | 64bit Address; 64bit Data, Time Multiplexed |
| System Bus: | 2bits; Clock/Reset |
| Interface Control Bus: | 7bits; Ready, Acknowledge, Stop |
| Parity Bus: | 2 bits, 1 for the 32 LSBs and 1 for the 32 MSB bits |
| Errors Bus: | 2 bits, 1 for Parity and 1 for System |
| Command/Byte Enable: | 8 bits (0-3 @ 32bit, and 4-7@ 64bit Bus) |
| 64MHz Control: | 6 bits; (2) Enable/Running, (2) Present, (2) Ack/Req |
| Cache Size: | 2 Bits |
| Interrupt bus: | 4 bits |
| JTAG Serial Bus: | 5 Bits |
| Power Supply: | +5, +3.3, +12, -12v, GND |
The Time Multiplexed Address and Data bus may exist as either 0 to 31
bits (32bits) or 0 to 63 bits (64bits) using the 64 bit expansion bus.
Both the Address and Data line use the same bus, Address first then Data.
32 bit PCI may also use 64 bit addressing by using two address cycles;
termed Dual Address Cycles (DAC), the low order address is sent first.
Additional control bits are utilized once the bus is increased to 64
bits.
The specification defines both a Reset line and a Clock line. The Clock
may be either 33MHz or 66MHz. I believe the 66MHz clock rate is only
defined for the 64bit bus width.
A number of 'Handshake' lines exist to allow communication, i.e. Ready,
and Acknowledge, see pinout above.
Two Parity lines are made available, one for the 32 bit bus width (bits 0
to 31) and an additional one for the 64 bit expansion (bits 32 to 63).
Two error bits; I assume, 1 for the LSB 32 bits and one for the upper 32
bits.
The pinout listings showing (+5 V or +3.3 V) mean: In a +5 volt system
the pins are +5 volts, in a +3.3 volt system the pins are +3.3 volts.
Back to the main PCI Bus page, or the PCI Board Dimension page PCI Card Size or Personal Computer bus page.
The Peripheral Component Interface 'PCI' Bus was originally developed as a local bus expansion for the PC (ISA) bus. The PCI spec defines the Electrical requirements for the interface. No bus terminations are specified, the bus relies on signal reflection to achieve level threshold. The first version of the PCI bus ran at 33MHz with a 32 bit bus (133MBps), the current version runs at 66MHz with a 64 bit bus. The PCI bus operates either synchronously or asynchronously with the mother board bus rate. While operating asynchronously the bus will operate at any frequency from 66MHz down to (and including) 0Hz. Flow control is added to allow the bus to operate with slower devices on the bus, allowing the bus to operate at their speed. PCI is an unterminated bus, the signal relay on signal reflections to attain there final value.
Engineering Key words: Peripheral Component Interface, PCI pinout, PCI Parallel Bus Pinouts, Pin Description, Pin Out, pinout, Connector, Signal Names, Pin-Names, Pin Number, Assignment, Specification, Standard, Defined, Constraint, Properties, Lines, Data, Labels, Description, Peripheral Component Interface, Personal Computer Local Bus.
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