PCI-Express 4x Connector Pin Out

The PCI-Express bus supports 1x, 2x, 4x [10Gbps], 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs].
The PCI-Express [PCIe] 4x signal names and pinout are listed in the table below.
The 4x wide PCI Express bus is not used on main-stream PC motherboards.
Links to additional PCI Express pinout widths are listed after the table.

PCI-Express 4x PinOut
Pin Side B Connector Side A Connector
# name Description name Description
1 +12v +12 volt power PRSNT#1 Hot plug presence detect
2 +12v +12 volt power +12v +12 volt power
3 RSVD Reserved +12v +12 volt power
4 GND Ground GND Ground
7 GND Ground JTAG4 TDO
8 +3.3v +3.3 volt power JTAG5 TMS
9 JTAG1 +TRST# +3.3v +3.3 volt power
10 3.3Vaux 3.3v volt power +3.3v +3.3 volt power
11 WAKE# Link Reactivation PWRGD Power Good
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ Reference Clock
Differential pair
14 HSOp(0) Transmitter Lane 0,
Differential pair
15 HSOn(0) GND Ground
16 GND Ground HSIp(0) Receiver Lane 0,
Differential pair
17 PRSNT#2 Hotplug detect HSIn(0)
18 GND Ground GND Ground
19 HSOp(1) Transmitter Lane 1,
Differential pair
RSVD Reserved
20 HSOn(1) GND Ground
21 GND Ground HSIp(1) Receiver Lane 1,
Differential pair
22 GND Ground HSIn(1)
23 HSOp(2) Transmitter Lane 2,
Differential pair
GND Ground
24 HSOn(2) GND Ground
25 GND Ground HSIp(2) Receiver Lane 2,
Differential pair
26 GND Ground HSIn(2)
27 HSOp(3) Transmitter Lane 3,
Differential pair
GND Ground
28 HSOn(0) GND Ground
29 GND Ground HSIp(3) Receiver Lane 3,
Differential pair
30 RSVD Reserved HSIn(3)
31 PRSNT#2 Hot plug detect GND Ground
32 GND Ground RSVD Reserved

The PCI Express specification is the new serial bus addition to the PCI series of specifications. This is a serial bus which uses two low-voltage differential LVDS pairs, at 2.5Gb/s in each direction [one transmit, and one receive pair]. PCI Express uses 8B/10B encoding [each 8 bit byte is translated into a 10 bit character in order to equalize the numbers of 1's and 0's sent, and the encoded signal contains an embedded clock]. PCI Express supports 1x [2.5Gbps], 2x, 4x, 8x, 12x, 16x, and 32x bus widths [transmit / receive pairs]. The PCI-Express [PCIe] 1x signal names and pinout are listed above.

The differential pins [Lanes] listed in the pin out table above are LVDS which stands for: Low Voltage Differential Signaling. The Electrical layer of LVDS is described on the LVDS bus page.
The function of the JTAG pins listed above are described on the JTAG bus page. The function of the SMbus pins listed above are described on the SMbus page.

PCIe Pinout Definitions:
PCI-Express 1x Connector Pinout and 1x signal names.
PCI-Express 8x Connector Pinout and 8x signal names.
PCI-Express 16x Connector Pinout and 16x signal names.
The main PCI-Express PCIe bus page.

Editor note; never connect to a signal any time you see a notation about a pin being unused, not used or reserved [RSVD]. The PCIe pin out table contains a number of lines that indicate reserved. Trying to send another ground line or some other signal into a pin not being used is just asking for trouble. Although rare, pins do change functionality in later versions of some standards. When the pin is currently unused, or not to be used, as in the case of a reserved pin may indicate a potential use in a later update.

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Modified 3/05/12
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