## Digital Logic metastability

### Terms of Digital Logic metastability Definition

Definitions listed in Logical order.
Problem: Introducing an asynchronous signal into a digital {synchronized} system, using Flip-Flops.
The outcome is Intermittent or random failures during operation.

How to avoid metastability in ICs: Add an additional Flip Flop in the design to Synchronize the incoming
asynchronous signal with the new clock domain, which will reduce the Mean-Time-Between-Failure [MTBF].

metastable: A state which exist between either "valid" digital logic state {an undefined voltage}

Digital Logic State: A defined range of voltages that indicate which logic level the device will switch to, or resides in.
For TTL, a logic low is {0 to .8 volts}, a logic high is {2.4 to 5 volts} [Logic Threshold Voltage Levels].

Undefined Voltage: A voltage between the established logic level, either High or Low; {.8 to 2.4 volts} from the example above.

Set-Up Time The time required for the input data signal at a flip flop to be valid before the incoming clock edge arrives.
The time interval between the application of a signal that is maintained at a specified input terminal and a consecutive active transition at another specified input terminal.

Hold Time The time required for the input data signal to remain valid after the clock edge as transitioned.
The interval during which a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal.

Resolve Time: The amount of time the Flip Flop's output must return to a valid level before it's used.
This is 1/{clock frequency} - path delay. The output must be valid by the next clock, minus any chip or routing delay.
Path Delay = Tcko + Troute + Tsu;
.... Tcko = Clock to Output time of the flip flop,
.... Troute = Any trace delay between the the Q of the flip flop and the next device reading that data,
.... Tsu = any Set-Up time required by the next device reading the data.

Skew {Clock or data}: The change in time of one signal compared to another, caused by timing delays or
propagation delays. ~The timing differences developed by different devices performing the same function.

Ambiguity: The uncertainty in the amount of time it takes for a valid logic signal
to change from one state to another.

metastability Window: The specific length of time, during which both the data
and clock should not occur. If both signals do occur, the output may go metastable.

 Device t(set-up) nS t(hold) nS t(total) nS 74C74 100.0 0.0 100.0 74HC74 20.0 0.0 20.0 74HCT74 20.0 0.0 20.0 7474 20.0 5.0 25.0 74ALS74 15.0 10.0 25.0 74LS74 20.0 0.0 20.0 74S74 3.0 2.0 5.0 74LS74 4.5 0.0 4.5 74AC74 4.0 0.5 4.5 74ACT74 3.0 1.0 4.0 74ACTQ74 3.0 1.5 4.5

The Table above shows various Set-Up times and Hold times for a number different Logic families. The combination of the two values determine the width of the metastability window.
The larger the window, the greater the chance the device will go metastable.
In most cases newer logic families have smaller metastability windows which reduce the chance of the device going metastable.

{Digital Logic metastability Index}

### Input Waveforms

 A single stage Flip Flop [acting as a Synchronizer]. The absolute minimum a design should provide. One stage may be enough, if the incoming data frequency is "slow", and the Flip Flop family is "fast". If the chosen Flip Flop has time to resolve the metastable condition before the next clock tick, and the output of the FF does not go to an asynchronous gate - the design may be solid. The time between the two white lines in the diagram below defines the metastability window or Timing Violation.

The diagram above shows the flip flop clock and three possible times [zones] the data may arrive at the Flip Flop [FF].
Data input 'Da' arrives and becomes stable before the clock edge.
Data 'Db' arrives just before the clock edge violating the flip flops set-up time.
Data 'Dc' changes [or arrives after] the clock edge violating the hold time of the flip flop.

### Output Waveforms

 Output waveforms due to signal timing Da, Db, Dc 'Da' produces a normal output, as the data does not violate the Set-up or Hold time of the device [in relation to the clock]. Either 'Db' or 'Dc' may produce a metastable output forcing the output to stay undefined for a longer amount of time, increasing the propagation delay of the Flip Flop.

Five possible conditions exist:
One: No timing violation occurred, and the output moves to the appropriate state (high or low).
Two: A timing violation does occur, and the output oscillates between the valid states (for a long time), or until its needed.
Third: A timing violation does occur, and the output moves to the wrong state.
Forth: A timing violation does occur, and the propagation delay is increased. Causing the next device in the chain to see the wrong value.
Fifth: A timing violation does occur, and no meta-stable behavior occurs. The output moves to the correct state with no oscillation or increase in propagation delay.
However this condition is problematic because the gamble is taken each time the device is clock. This condition may persist for thousands of clock cycles, but may fail on the next clock cycle.
For a fail-safe design stay in condition one, any other condition will result in failure.

{Digital Logic metastability Index}

### Multi-Stage Synchronizer

 Single stage Flip Flop vs. Dual stage Flip Flop: Adding a second Flip Flop to the design will reduce the chance of the output going metastable. The output from the first flip flop may go valid, before the second flip flop is clocked. The graph shows data for both a 1-stage [1 flip flop] and 2-stage synchronizer [2 flip flops]. A 74AS4374 from TI provides a 'D' type, Dual stage synchronizer. Adding a third flip flop will reduce the probability that its output will be unstable even more. Although a 3-stage synchronizer is not shown in the data. Although not indicated, the data points will shift with different logic families. As each different logic family has their own MTBF, based on switching speed. Note the chart is dated, 70MHz is relatively slow speed.

The table above details the difference in MTBF between a Single and Dual stage synchronizer.
The graph below shows the difference between the different logic families, based on clocking data into a flip flop.

The two graphs above, develop from a Texas Instruments Power Point presentation, details many of the standard TTL families.

{Digital Logic metastability Index}

### metastability Equations

To determine how often a Flip Flop will go to an undefined state, plug the data into one of these equations to calculate the MTBF.
The first equation is the general calculation, while the second uses a worst case input data rate of half the clock frequency.

metastability Definitions

MTBF: Mean Time Between Failure
FD: Data Frequency
FC: Clock Frequency
TP: Flip Flop Propagation Delay
tr: Resolve Time
dt: Delay Time between Clocks [symbol delta t]
tsu: Device Setup Time
g: Flip FLop Resolution Time [symbol gama]

These are device dependent. Resolve time (among others) has to be looked up, via the data sheet (if it's provided).
As a rule: The faster the flip flop used, the better the MTBF for a given circuit.
The faster device families have lower Set-up and Hold times. This reduces the window of occurrence.

{Back to Digital Logic metastability Index}

metastability in Altera Devices [Altera: www.altera.com/literature/an/an042.pdf]

metastability Performance of Clocked FIFOs [TI: http://focus.ti.com/lit/an/scza004a/scza004a.pdf]

metastability and the ECLinPS Family [ON Semiconductor: www.onsemi.com/pub/Collateral/AN1504-D.PDF]

{Digital Logic metastability Index}

### MTBF Examples

PLDs Timing

While reviewing the data in the table, keep in mind that the information is some what dated.
I'm sure the newer FPGAs and PLD ICs have MTBF [Mean-Time-Between-Failure] numbers which far exceed the ones listed.
A previous Check the Cypress site found that their faster version of a 22V10 IC is a dash five (5 nS).

 Device fmax (MHz) W(fsec) tsw(nsec) tr(nsec)(10-year MTBF) PALC16R8-25 28.5 9.503 0.515 14.68 PALC20G10-20 41.6 3.73 0.173 4.91 PALC20RA10-15 33.3 2.86 0.216 5.87 PALC22V10C-10 90.9 0.00808 0.547 13.0 PALC22V10B-15 50.0 55.76 0.261 8.19 PALC22V10-20 41.6 0.125 0.190 4.73 CY7C330-66 66.6 1.02 0.290 8.12 CY7C331-20 31.2 298.0 0.184 5.91 CY7C332-15 47.6 1.55 0.337 9.35 CY7C344-20 41.6 966.0 0.223 7.55

The Table data was copied from "Determine PLD metastability to derive ample MTBFs",
EDN August 5 1991, Author: Sean Dingman.
2/2/10 note that many of these data sheets are still available as products and dated around 1992.

FPGA: Field Programmable Gate Array
PLD: Programmable Logic Devices
PLA Programmable Logic Array
GAL Generic Array Logic
MACH high density PLD
CPLD Complex PLD
Programmable Devices Manufacturers

Use the Design icon below for more engineering hints on Logic Design and Logic Hazards.

Definitions:
What is a Glitch.
Logic Noise Margin.
Logic Propagation Delay.

{Back to metastability Index}

Modified 6/13/15