Glue Logic Timing Hazards

A Static Hazard is defined when a single variable change at the input causes a momentary change in another variable [the output]. A Dynamic Hazard occurs when a change in the input causes multiple changes in the output [i.e. from 1 to 0 and back to 1]. In either case of a Static or Dynamic hazard the product produced is an unanticipated glitch [the hazard]. The resulting glitches in the circuit may or may not induce additional problems ~ other then increased issues due to switching noise. However; a problem may occur if the signal with the glitch is a clock line. A glitch on the clock line to a flip flop will cause device to clock in data when it wasn't meant to. A glitch on a clock line of a counter will also have a negative effect. In any case, good design practice means designing out these hazards.

There are two types of Static hazards: the high output transitions to a low and back high [a low going glitch]. Or the low output transitions to a high [1] and back low [0] [a high going glitch]. There are also two types of Dynamic hazards: the 0 output transitions to a 1 back to 0 and then 1 again. Or the 1 output transitions to a 0 back to 1 and then 0 again.

If Static Hazards are removed from the design, Dynamic Hazards will not occur. A Karnaugh map [K-map] is the easiest way to eliminate a Static Hazard or glitch. These timing hazards will develop as random or intermittent circuit failures. The type of circuit failure will depend on the signals used in the AND / OR gate circuit, and perhaps how often they change state. Another method to eliminate timing hazards from effecting an IC down the line is to re-clock the final output signals. Re-clocking the signal does not eliminate the glitch, but stops it from causing circuit failure. Re-clocking the signal seems to be common for designers unsure of why the glitch occurs, or how to stop the glitch from developing. Solving the problem via a K-map results in an additional AND gate, re-clocking requires an additional flip flop.

Karnaugh map eliminating Static Hazards

A K-map for each combinatorial logic function which has an output should be used. Redundant prime implicants should be added to the K-Map (circuit) [shown in RED above], which will guarantee that all single-bit input changes are covered. Multi-level functions will be reduced to "two-level" functions, and analyzed by the K-map approach. The procedure for designing a static-hazard-free network is a straightforward application. The key is to place the function in such a form that the transient output function guarantees that every set of adjacent 1's in the K-map are covered by a term, and that no terms contain both a variable and its complement. The former condition eliminates 1-hazards and the latter eliminates 0-hazards. Dynamic hazards happen because of multiple paths in a multilevel network, each with its own asymmetric delay. Circuits which contain multiple paths of the same signal should be re-clocked before the signal is used by a circuit.

Static 0 hazards occur in 'Product-Of-Sums' [POS] implementations, but do not occur in 'Sum-Of-Products' [SOP] implementations. Static 1 hazards occur in SOP implementations, do not occur in POS implementations.
How to avoid logic hazards: develop a Karnaugh map [K-map].

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Modified 3/05/12
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